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MK1728-01GTRLF PDF预览

MK1728-01GTRLF

更新时间: 2024-01-23 06:35:40
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
8页 210K
描述
Clock Generator, 36MHz, CMOS, PDSO8, TSSOP-8

MK1728-01GTRLF 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:TSSOP-8
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.4 mm
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:36 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED主时钟/晶体标称频率:36 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

MK1728-01GTRLF 数据手册

 浏览型号MK1728-01GTRLF的Datasheet PDF文件第1页浏览型号MK1728-01GTRLF的Datasheet PDF文件第2页浏览型号MK1728-01GTRLF的Datasheet PDF文件第4页浏览型号MK1728-01GTRLF的Datasheet PDF文件第5页浏览型号MK1728-01GTRLF的Datasheet PDF文件第6页浏览型号MK1728-01GTRLF的Datasheet PDF文件第7页 
MK1728-01  
2.5 VOLT LOW EMI CLOCK GENERATOR  
SSCG  
External Components  
The MK1728-01 requires a minimum number of external  
components for proper operation.  
same side of the board, minimizing vias through other signal  
layers. Other signal traces should be routed away from the  
MK1728-01. This includes signal traces just underneath the  
device, or on layers adjacent to the ground plane layer used  
by the device.  
Decoupling Capacitor  
A decoupling capacitor of 0.01µF must be connected  
between VDD and GND on pins 2 and 3, as close to these  
pins as possible. For optimum device performance, the  
decoupling capacitor should be mounted on the component  
side of the PCB. Avoid the use of vias in the decoupling  
circuit.  
Crystal Information  
The crystal used should be a fundamental mode (do not use  
third overtone), parallel resonant. Crystal capacitors should  
be connected from pins X1 to ground and X2 to ground to  
optimize the initial accuracy. The value of these capacitors  
is given by the following equation:  
Series Termination Resistor  
When the PCB trace between the clock output and the load  
is over 1 inch, series termination should be used. To series  
terminate a 50trace (a commonly used trace impedance)  
place a 33resistor in series with the clock line, as close to  
the clock output pin as possible. The nominal impedance of  
the clock output is 20.  
Crystal caps (pF) = (C - 6) x 2  
L
In the equation, C is the crystal load capacitance. So, for a  
L
crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2]  
capacitors should be used.  
Tri-level Select Pin Operation  
The S1 and S0 select pins are tri-level, meaning they have  
three separate states to make the selections shown in the  
table on page 2. To select the M (mid) level, the connection  
to these pins must be eliminated by either floating them  
originally, or tri-stating the GPIO pins which drive the select  
pins.  
Spread Spectrum Profile  
The MK1728-01 low EMI clock generator uses an optimized  
frequency slew rate algorithm to facilitate down stream  
tracking of zero delay buffers and other PLL devices. The  
frequency modulation amplitude is constant with variations  
of the input frequency.  
PCB Layout Recommendations  
For optimum device performance and lowest output phase  
noise, the following guidelines should be observed.  
1) The 0.01µF decoupling capacitor should be mounted on  
the component side of the board as close to the VDD pin as  
possible. No vias should be used between the decoupling  
capacitor and VDD pin. The PCB trace to VDD pin should  
be kept as short as possible, as should the PCB trace to the  
ground via.  
Modulation Rate  
2) To minimize EMI, the 33series termination resistor (if  
needed) should be placed close to the clock output.  
Time  
3) An optimum layout is one with all components on the  
IDT™ / ICS™ 2.5 VOLT LOW EMI CLOCK GENERATOR  
3
MK1728-01  
REV A 081204  

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