Document Number: IMX8QXPAEC
Rev. 2, 03/2020
NXP Semiconductors
Data Sheet: Technical Data
MIMX8QXnAVxFZAC
MIMX8DXnAVxFZAC
i.MX 8QuadXPlus and
8DualXPlus Automotive
and Infotainment
Package Information
21 x 21 mm package case outline
17 x 17 mm package case outline
Applications Processors
Ordering Information
See Section 1.1Table 2 on page 5
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 System Controller Firmware (SCFW) Requirements6
1.3 Package options . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 16
3.2 Recommended Connections for Unused Interfaces16
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Power supplies requirements and restrictions. . . . 27
4.3 PLL electrical characteristics. . . . . . . . . . . . . . . . . 30
4.4 On-chip oscillators. . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36
4.6 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 43
4.7 Output Buffer Impedance Parameters. . . . . . . . . . 45
4.8 System Modules Timing . . . . . . . . . . . . . . . . . . . . 50
4.9 General-Purpose Media Interface (GPMI) Timing. 54
4.10 External Peripheral Interface Parameters . . . . . . . 63
4.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 111
Boot mode configuration. . . . . . . . . . . . . . . . . . . . . . . . 114
5.1 Boot mode configuration pins . . . . . . . . . . . . . . . 114
5.2 Boot devices interfaces allocation. . . . . . . . . . . . 114
Package information and contact assignments . . . . . . 116
6.1 FCPBGA, 21 x 21 mm, 0.8 mm pitch . . . . . . . . . 116
6.2 FCPBGA, 17 x 17 mm, 0.8 mm pitch . . . . . . . . . 133
Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
1 Introduction
This data sheet contains specifications for the
i.MX 8QuadXPlus and 8DualXPlus processors, which,
along with the i.MX 8DualX processor , comprise the
i.MX 8X Family (for i.MX 8DualX specifications, see
i.MX 8DualX Automotive and Infotainment Processors
[IMX8DXAEC]). The i.MX 8X processors consist of
2
3
4
®
three to five Arm cores (two to four Arm Cortex -A35
®
and one Cortex -M4F). All devices include separate
GPU and VPU subsystems as well as a failover-ready
display controller. Advanced multicore audio processing
is supported by the Arm cores and a high performance
®
Tensilica HiFi 4 DSP for pre- and post-audio
processing as well as voice recognition. The i.MX 8X
Family supports up to three displays with multiple
display output options, including parallel, MIPI-DSI,
and LVDS. Memory interfaces for this device include:
5
6
7
•
•
•
•
LPDDR4 (no error correcting code [ECC])
DDR3L (optional ECC)
2× Quad SPI or 1× Octal SPI (FlexSPI)
eMMC 5.1, RAW NAND, and SD 3.0
NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of
its products.
© 2018-2020 NXP B.V.