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MH8S72BALD-6 PDF预览

MH8S72BALD-6

更新时间: 2024-02-16 09:48:12
品牌 Logo 应用领域
三菱 - MITSUBISHI /
页数 文件大小 规格书
40页 582K
描述
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MH8S72BALD-6 数据手册

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MITSUBISHI LSIs  
MH8S72BALD-6  
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM  
PRELIMINARY  
Some of contents are subject to change without notice.  
DESCRIPTION  
The MH8S72BALD is 8388608 - word x 72-bit Synchronous  
DRAM module. This consist of nine industry standard 8M x  
8 Synchronous DRAMs in TSOP.  
The TSOP on a card edge dual in-line package provides any  
application where high densities and large of quantities  
memory are required.  
85pin  
1pin  
This is a socket-type memory module ,suitable for easy  
interchange or addition of module.  
FEATURES  
Max.  
Frequency  
Access Time from CLK  
[component level]  
94pin  
95pin  
10pin  
11pin  
Type name  
5.4ns  
(CL = 3)  
MH8S72BALD-6  
133MHz  
Utilizes industry standard 8M X 8 Synchronous DRAMs in TSOP  
package  
Single 3.3V +/- 0.3V supply  
Max.Clock frequency 133MHz  
Fully synchronous operation referenced to clock rising edge  
4-bank operation controlled by BA0,BA1(Bank Address)  
/CAS latency -2/3(programmable,at buffer mode)  
LVTTL Interface  
124pin  
125pin  
40pin  
41pin  
Burst length 1/2/4/8/Full Page(programmable)  
Burst type- Sequential and interleave burst (programmable)  
Random column access  
Burst Write / Single Write(programmable)  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
4096 refresh cycles every 64ms  
APPLICATION  
84pin  
168pin  
Main memory or graphic memory in computer systems  
11/May. /1999  
MIT-DS-0316-0.0  
MITSUBISHI  
ELECTRIC  
1

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