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MH74S00 PDF预览

MH74S00

更新时间: 2024-10-28 22:16:43
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
18页 588K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

MH74S00 数据手册

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SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003  
D
Package Options Include Plastic  
Small-Outline (D, NS, PS), Shrink  
Small-Outline (DB), and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J) DIPs  
D
Also Available as Dual 2-Input  
Positive-NAND Gate in Small-Outline (PS)  
Package  
SN5400 . . . J PACKAGE  
SN54LS00, SN54S00 . . . J OR W PACKAGE  
SN7400, SN74S00 . . . D, N, OR NS PACKAGE  
SN74LS00 . . . D, DB, N, OR NS PACKAGE  
(TOP VIEW)  
SN74LS00, SN74S00 . . . PS PACKAGE  
(TOP VIEW)  
V
2B  
2A  
2Y  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1
2
3
4
8
7
6
5
1A  
1B  
1Y  
CC  
4B  
4A  
4Y  
3B  
3A  
3Y  
GND  
2Y  
GND  
8
SN5400 . . . W PACKAGE  
(TOP VIEW)  
SN54LS00, SN54S00 . . . FK PACKAGE  
(TOP VIEW)  
1A  
1B  
1Y  
4Y  
4B  
4A  
GND  
3B  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
3
2 1 20 19  
18  
4A  
NC  
4Y  
NC  
3B  
1Y  
NC  
2A  
4
5
6
7
8
V
17  
16  
15  
14  
CC  
2Y  
2A  
2B  
3A  
3Y  
NC  
2B  
8
9 10 11 12 13  
NC − No internal connection  
description/ordering information  
These devices contain four independent 2-input NAND gates. The devices perform the Boolean function  
Y = A B or Y = A + B in positive logic.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢓ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢭꢑ ꢆꢐ ꢍꢌ ꢮ ꢐꢯꢰꢂ ꢯꢂꢅ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
ꢡ ꢘꢥ ꢢꢟꢟ ꢚ ꢞꢨꢢ ꢛ ꢪꢗ ꢟꢢ ꢘ ꢚꢞꢢ ꢦꢧ ꢓ ꢘ ꢝꢥ ꢥ ꢚ ꢞꢨꢢ ꢛ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢟ ꢅ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚ ꢘ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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