Datasheet > MCZ33905BD3EK

MCZ33905BD3EK

更新时间： 2024-01-18 18:37:09

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
8页	278K
描述
3.3V SBC HSCAN DUAL LIN

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数据手册

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MCZ33905BD3EK 数据手册

Analog, Mixed-Signal and Power Management

MC33903/4/5

System Basis Chip Gen2 with High Speed CAN and

LIN Interface

Overview

The MC33903/4/5 is the second generation

family of System Basis Chips, which combine

several features and enhance present module

designs. The device works as an advanced

MC33903/4/5 Block Diagram

MCU Voltage Regulator (V_DD)

power management unit for the MCU and

additional integrated circuits such as sensors

Internal CAN Regulator (V_CAN

)

and CAN transceivers. It has a built-in enhanced

high speed CAN interface (ISO11898-2 and -5),

with local and bus failure diagnostics, protection,

and fail safe operation mode. The SBC may

include one or two LIN 2.1/J2602-2 interfaces

with LIN master terminal outputs. It includes

wake-up input pins than can also be configured

as output drivers for flexibility.

Legend

Low Power Modes

SPI Adv W/D

Secured State Machine

Flexible (I/O)

33903

33903S

33903D

33904

This device implements multiple Low Power

modes with very low-current consumption. In

addition, the device is part of a family concept

where pin compatibility, among the various

devices with and without LIN interfaces, adds

versatility to module design.

CAN High Speed

Power Sharing (V_DDBALLAST)

33905S

33905D

Ballast Regulator (V_AUX

LIN 1

)

The MC33903/4/5 also implements an

innovative and advanced fail-safe state machine

and concept solution. This family of devices are

supported by an enablement ecosystem that

includes an evaluation board, software interface,

EMC/ESD conformance reports and training

material that allows a faster time to market and

eases your designs.

LIN 2

12 3 4 5 6 7 8

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