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MCR03EZPFX3481 PDF预览

MCR03EZPFX3481

更新时间: 2024-11-05 12:46:39
品牌 Logo 应用领域
英飞凌 - INFINEON 稳压器双倍数据速率
页数 文件大小 规格书
32页 740K
描述
HIGHLY EFFICIENT INTEGRATED SYNCHRONOUS BUCK REGULATOR FOR DDR APPLICATIONS

MCR03EZPFX3481 数据手册

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PD-97508  
IR3832WMPbF  
TM  
SupIRBuck  
HIGHLY EFFICIENT INTEGRATED  
SYNCHRONOUS BUCK REGULATOR FOR DDR APPLICATIONS  
Features  
Description  
The IR3832W SupIRBuckTM is an easy-to-use,  
fully integrated and highly efficient DC/DC  
regulator. The MOSFETS co-packaged with the  
on-chip PWM controller make IR3832W a space-  
efficient solution, providing accurate power  
delivery for DDR memory applications.  
Wide Input Voltage Range 1.0V to 16V  
Wide Output Voltage Range 0.6V to 0.9*Vin  
Continuous 4A Load Capability  
Integrated Bootstrap-diode  
High Bandwidth E/A for excellent transient  
performance  
Programmable Switching Frequency up to 1.5 MHz  
Programmable Over Current Protection  
PGood output  
IR3832W is configured to generate termination  
voltage (VTT) for DDR memory applications.  
Hiccup Current Limit  
IR3832W offers programmability of start up time,  
switching frequency and current limit while  
operating in wide input and output voltage range.  
Programmable Soft-Start  
Enable Input with Voltage Monitoring Capability  
Enhanced Pre-Bias Start-up  
The switching frequency is programmable from  
250kHz to 1.5MHz for an optimum solution.  
Vp input for DDR Tracking applications  
-40oC to 125oC operating junction temperature  
Thermal Protection  
It also features important protection functions,  
such as Pre-Bias startup, hiccup current limit and  
thermal shutdown to give required system level  
security in the event of fault conditions.  
5mm x 6mm Power QFN Package, 0.9 mm height  
Halogen Free, Lead Free and RoHS Compliant  
Applications  
Server Applications  
Distributed Point of Load Power Architectures  
Netcom Applications  
Storage Applications  
Embedded Telecom Systems  
1.0V <Vin<16V  
4.5V <Vcc<5.5V  
Enable  
Vin  
Boot  
Vo  
Vcc  
VDDQ  
SW  
PGood  
PGood  
OCSet  
Fb  
Vp  
Rt  
Comp  
PGnd  
SS/ SD  
Gnd  
Fig. 1. Typical application diagram  
1
Rev 6.0  

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