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MCP4921T-E/SL PDF预览

MCP4921T-E/SL

更新时间: 2024-10-27 04:40:19
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美国微芯 - MICROCHIP /
页数 文件大小 规格书
42页 3213K
描述
12-Bit DAC with SPI⑩ Interface

MCP4921T-E/SL 数据手册

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MCP4921/4922  
12-Bit DAC with SPI™ Interface  
Features  
Description  
• 12-Bit Resolution  
The Microchip Technology Inc. MCP492X are 2.7 –  
5.5V, low-power, low DNL, 12-Bit Digital-to-Analog Con-  
verters (DACs) with optional 2x buffered output and SPI  
interface.  
• ±0.2 LSB DNL (typ)  
• ±2 LSB INL (typ)  
• Single or Dual Channel  
The MCP492X are DACs that provide high accuracy  
and low noise performance for industrial applications  
where calibration or compensation of signals (such as  
temperature, pressure and humidity) are required.  
• Rail-to-Rail Output  
• SPI™ Interface with 20 MHz Clock Support  
• Simultaneous Latching of the Dual DACs w/LDAC  
• Fast Settling Time of 4.5 µs  
• Selectable Unity or 2x Gain Output  
• 450 kHz Multiplier Mode  
The MCP492X are available in the extended tempera-  
ture range and PDIP, SOIC, MSOP and TSSOP  
packages.  
The MCP492X devices utilize a resistive string archi-  
tecture, with its inherent advantages of low DNL error,  
low ratio metric temperature coefficient and fast settling  
time. These devices are specified over the extended  
temperature range. The MCP492X include double-  
buffered inputs, allowing simultaneous updates using  
the LDAC pin. These devices also incorporate a  
Power-On Reset (POR) circuit to ensure reliable  
power-up.  
• External VREF Input  
• 2.7V to 5.5V Single-Supply Operation  
• Extended Temperature Range: -40°C to +125°C  
Applications  
• Set Point or Offset Trimming  
• Sensor Calibration  
• Digitally-Controlled Multiplier/Divider  
• Portable Instrumentation (Battery-Powered)  
• Motor Feedback Loop Control  
Package Types  
8-Pin PDIP, SOIC, MSOP  
Block Diagram  
V
V
1
2
3
4
8
7
6
5
DD  
OUTA  
CS  
SDI  
SCK LDAC  
AV  
V
CS  
SCK  
SDI  
SS  
REFA  
VDD  
Power-on  
Reset  
LDAC  
Interface Logic  
AVSS  
Input  
Input  
14-Pin PDIP, SOIC, TSSOP  
Register A Register B  
V
V
V
1
14  
DD  
OUTA  
REFA  
NC  
CS  
2
3
4
13  
12  
11  
DACA  
Register  
DACB  
Register  
AV  
V
SS  
VREF  
B
VREF  
A
SCK  
REFB  
String  
DACB  
String  
DACA  
V
5
6
7
10  
9
SDI  
NC  
NC  
OUTB  
SHDN  
LDAC  
Buffer  
Buffer  
Gain  
Logic  
8
Gain  
Logic  
Output  
Op Amps  
Output  
Logic  
VOUTA  
VOUTB  
SHDN  
© 2007 Microchip Technology Inc.  
DS21897B-page 1  

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