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MCM64Z916ZP10R PDF预览

MCM64Z916ZP10R

更新时间: 2024-11-21 20:20:27
品牌 Logo 应用领域
恩智浦 - NXP 静态存储器内存集成电路
页数 文件大小 规格书
34页 738K
描述
512KX18 ZBT SRAM, 10ns, PBGA119, PLASTIC, BGA-119

MCM64Z916ZP10R 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:BGA
包装说明:PLASTIC, BGA-119针数:119
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.53
Is Samacsys:N最长访问时间:10 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHTECTUREI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119长度:22 mm
内存密度:9437184 bit内存集成电路类型:ZBT SRAM
内存宽度:18湿度敏感等级:1
功能数量:1端子数量:119
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA119,7X17,50
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:2.5 V认证状态:Not Qualified
座面最大高度:2.4 mm最大待机电流:0.01 A
最小待机电流:2.3 V子类别:SRAMs
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

MCM64Z916ZP10R 数据手册

 浏览型号MCM64Z916ZP10R的Datasheet PDF文件第2页浏览型号MCM64Z916ZP10R的Datasheet PDF文件第3页浏览型号MCM64Z916ZP10R的Datasheet PDF文件第4页浏览型号MCM64Z916ZP10R的Datasheet PDF文件第5页浏览型号MCM64Z916ZP10R的Datasheet PDF文件第6页浏览型号MCM64Z916ZP10R的Datasheet PDF文件第7页 
Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
MOTOROLA  
Order this document  
by MCM64Z834/D  
MCM64Z834  
MCM64Z916  
Product Preview  
256K x 36 and 512K x 18 Bit  
ZBTr Fast Static RAM  
The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide  
Zero Bus Turnaroundr. The ZBT RAM allows 100% use of bus cycles during  
back–to–back read/write and write/read cycles. The MCM64Z834 (organized as  
256K words by 36 bits) and the MCM64Z916 (organized as 512K words by 18  
bits) are fabricated in Motorola’s high performance silicon gate CMOS tech-  
nology. This device integrates input registers, an output register, a 2–bit address  
counter, and high speed SRAM onto a single monolithic circuit for reduced parts  
count in communication applications. Synchronous design allows precise cycle  
control with the use of an external positive–edge–triggered clock (CK). CMOS  
circuitry reduces the overall power consumption of the integrated functions for  
greater reliability.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
ZP PACKAGE  
PBGA  
CASE 999–02  
Addresses (SA), data inputs (DQ), and all control signals except output enable  
(G) and linear burst order (LBO) are clock (CK) controlled through positive–  
edge–triggered noninverting registers.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (CK) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals. Write data is  
supplied to the memory one cycle after the write sequence initiation for the flow–  
throughdevice, andtwocyclesafterthewritesequenceinitiationforthepipelined  
device.  
For flow–through read cycles, the SRAM allows output data to simply flow freely from the memory  
array. For pipelined read cycles, the SRAM output data is temporarily stored by an edge–triggered  
output register and then released to the output buffers at the next rising edge of clock (CK).  
The MCM64Z834 and MCM64Z916 operate from a 2.5 V core power supply and all outputs oper-  
ate on a 2.5 V power supply. All inputs and outputs are JEDEC Standard JESD8–5 compatible.  
2.5 V ±200 mV Core Power Supply, 2.5 V I/O Supply  
MCM64Z834/916–10 = 10 ns Flow–Through Access/4 ns Pipelined Access (143 MHz)  
MCM64Z834/916–11 = 11 ns Flow–Through Access/4.2 ns Pipelined Access (133 MHz)  
MCM64Z834/916–15 = 15 ns Flow–Through Access/5 ns Pipelined Access (100 MHz)  
Selectable Read/Write Functionality (Flow–Through/Pipelined)  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Internally Self–Timed Write Cycle  
Two–Cycle Deselect (Pipelined)  
Byte Write Control  
ADV Controlled Burst  
Simplified JTAG  
100–Pin TQFP and 119–Bump PBGA Packages  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by  
Micron Technology, Inc. and Motorola, Inc.  
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 2  
9/20/99  
Motorola, Inc. 1999  
For More Information On This Product,  
Go to: www.freescale.com  

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