Datasheet > MCM63F837ZP7

MCM63F837ZP7

更新时间： 2024-11-11 11:05:59

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		/
页数	文件大小	规格书
28页	713K
描述
256K x 36 and 512K x 18 Bit Flow–Through BurstRAM Synchronous Fast Static RAM

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MCM63F837ZP7 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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MCM63F837

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MCM63F919

256K x 36 and 512K x 18 Bit

Flow–Through BurstRAM

Synchronous Fast Static RAM

The MCM63F837 and MCM63F919 are 8M–bit synchronous fast static RAMs

designed to provide a burstable, high performance, secondary cache for the

PowerPC and other high performance microprocessors. The MCM63F837

(organized as 256K words by 36 bits) and the MCM63F919 (organized as 512K

words by 18 bits) are fabricated in Motorola’s high performance silicon gate

CMOS technology. Synchronous design allows precise cycle control with the

use of an external clock (K).

TQ PACKAGE

TQFP

CASE 983A–01

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K)

controlled through positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM63F837 and MCM63F919

(burstsequenceoperatesinlinearorinterleavedmodedependentuponthestate

of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

ZP PACKAGE

PBGA

CASE 999–02

Synchronous byte write (SBx), synchronous global write (SGW), and

synchronous write enable (SW) are provided to allow writes to either individual

bytes or to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa,

SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx

are asserted with SW. All bytes are written if either SGW is asserted or if all SBx

and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

The MCM63F837 and MCM63F919 operate from a 3.3 V core power supply

and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs

are JEDEC standard JESD8–A and JESD8–5 compatible.

•

MCM63F837/MCM63F919–7 = 7 ns Access/8.5 ns Cycle (117 MHz)

MCM63F837/MCM63F919–8 = 8 ns Access/10 ns Cycle (100 MHz)

MCM63F837/MCM63F919–8.5 = 8.5 ns Access/11 ns Cycle (90 MHz)

3.3 V ±5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Single–Cycle Deselect Timing

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

Sleep Mode (ZZ)

Simplified JTAG

•

JEDEC Standard 100–Pin TQFP and 119–Bump PBGA Packages

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 1

8/23/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

MCM63F837•MCM63F919

For More Information On This Product,

Go to: www.freescale.com

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与MCM63F837ZP7相关器件

型号	品牌	获取价格	描述	数据表
MCM63F837ZP7R	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit Flow–Through Burs
MCM63F837ZP8	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit Flow–Through Burs
MCM63F837ZP8.5	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit Flow–Through Burs
MCM63F837ZP8.5R	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit Flow–Through Burs
MCM63F837ZP8R	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit Flow–Through Burs
MCM63F919	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit Flow–Through Burs
MCM63F919TQ7	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit Flow–Through Burs
MCM63F919TQ7R	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit Flow–Through Burs
MCM63F919TQ8	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit Flow–Through Burs
MCM63F919TQ8.5	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit Flow–Through Burs

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