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MCF51AG128CQH PDF预览

MCF51AG128CQH

更新时间: 2024-11-10 14:59:27
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
50页 1493K
描述
MCF51AG 32-bit MCU, ColdFire V1 core, 128KB Flash, 50MHz, QFP 64

MCF51AG128CQH 数据手册

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Freescale Semiconductor  
Data Sheet: Technical Data  
Document Number: MCF51AG128  
Rev. 5, 6/2010  
MCF51AG128  
80 LQFP  
64 LQFP  
MCF51AG128 ColdFire  
Microcontroller  
Covers: MCF51AG128 and  
MCF51AG96  
14 mm × 14 mm  
10 mm × 10 mm  
48 LQFP  
7 mm x 7mm  
64 QFP  
14 mm × 14 mm  
®
The MCF51AG128 is a member of the ColdFire family of  
– Low-voltage detection with reset or interrupt  
– Separate low voltage warning with selectable trip points  
– Illegal opcode and illegal address detection with reset  
– Flash block protection for each array to prevent  
accidental write/erasure  
32-bit variable-length reduced instruction set (RISC)  
microcontroller. This document provides an overview of the  
MCF51AG128 series MCUs, focusing on its highly  
integrated and diverse feature set.  
– Hardware CRC module to support fast cyclic  
redundancy checks  
• Debug Support  
The MCF51AG128 derivative are low-cost, low-power, and  
high-performance 32-bit ColdFire V1 microcontroller units  
(MCUs) designed for industrial and appliance applications. It  
is an ideal upgrade for designs based on the MC9S08AC128  
series of 8-bit microcontrollers.  
– Single-wire back ground debug interface  
– Real-time debug support, with six hardware breakpoints  
(4 PC, 1 address pair and 1 data) that can be configured  
into a 1- or 2-level trigger  
– On-chip trace buffer provides programmable start/stop  
recording conditions  
The MCF51AG128 features the following functional units:  
®
• 32-bit Version 1 ColdFire central processor unit (CPU)  
– Up to 50.33 MHz ColdFire CPU from 2.7 V to 5.5 V  
– Provide 0.94 Dhrystone 2.1 DMIPS per MHz  
performance when running from internal RAM (0.76  
DMIPS per MHz when running from flash)  
– Implements Coldfire Instruction Set Revision C  
(ISA_C)  
– Support for real-time program (and optional partial data)  
trace using the debug visibility bus  
• DMA Controller  
– Four independently programmable DMA channels  
provide the means to directly transfer data between  
system memory and I/O peripherals  
– DMA enabled peripherals include IIC, SCI, SPI, FTM,  
HSCMP, ADC, RTC, and eGPIO, and the DMA request  
from these peripherals can be configured as DMA  
source or as an iEvent input  
• On-chip memory  
– Up to 128 KB flash memory read/program/erase over  
full operating voltage and temperature  
– Up to 16 KB random access memory (RAM)  
– Security circuitry to prevent unauthorized access to  
RAM and flash contents  
• CF1_INTC  
• Power-Saving Modes  
– Support of 44 peripheral I/O interrupt requests and seven  
software (one per level) interrupt requests  
– Fixed association between interrupt request source, level  
and priority, up to two requests can be remapped to the  
highest maskable level and priority  
– Unique vector number for each interrupt source  
– Support for service routine interrupt acknowledge  
(software IACK) read cycles for improved system  
performance  
– Three ultra-low power stop modes and reduced power  
wait mode  
– Peripheral clock enable register can disable clocks to  
unused modules, thereby reducing currents  
• System Protection  
– Advanced independent clocked watchdog (WDOG)  
with features like, robust refresh mechanism, windowed  
mode, high granulation timeout, fast test of timeout, and  
always forces a reset  
– Additional external watchdog monitor (EWM) to help  
reset external circuits  
– Ability to mask any individual or all interrupt sources  
Freescale reserves the right to change the detail specifications as may be required to permit  
improvements in the design of its products.  
© Freescale Semiconductor, Inc., 2010. All rights reserved.  

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