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MC8610TVT800GB PDF预览

MC8610TVT800GB

更新时间： 2024-11-07 15:46:07
品牌 Logo 应用领域
恩智浦 - NXP 外围集成电路
页数 文件大小 规格书
96页 1137K
描述
IC,MICROPROCESSOR,32-BIT,BGA,783PIN,PLASTIC

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MC8610TVT800GB 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：BGA, BGA783,28X28,40
Reach Compliance Code：not_compliantECCN代码：3A991
HTS代码：8542.31.00.01风险等级：5.84
地址总线宽度：16位大小：32
边界扫描：YES外部数据总线宽度：64
格式：FIXED POINT集成缓存：YES
JESD-30 代码：S-PBGA-B783JESD-609代码：e2
长度：29 mm低功率模式：YES
湿度敏感等级：3端子数量：783
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA783,28X28,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：245
电源：1 V认证状态：Not Qualified
座面最大高度：2.7 mm速度：800 MHz
子类别：Microprocessors最大供电电压：1.05 V
最小供电电压：0.95 V标称供电电压：1 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver (Sn/Ag)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：29 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR, RISC
Base Number Matches：1

MC8610TVT800GB 数据手册

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Freescale Semiconductor  
Data Sheet  
Document Number: MPC8610EC  
Rev. 2, 01/2009  
MPC8610 Integrated Host Processor  
Hardware Specifications  
Features  
– Boot sequencer  
– Optionally loads configuration data from serial ROM at  
• High-performance, 32-bit e600 core, that implements the  
Power Architecture™ technology  
– Eleven execution units and three register files  
– Two separate 32-Kbyte instruction and data level 1 (L1)  
caches  
2
reset via I C interface  
– Can be used to initialize configuration registers and/or  
memory  
2
– Supports extended I C addressing mode  
• DUART  
• Fast InfraRed interface  
• Serial peripheral interface  
– Integrated 256-Kbyte, eight-way set-associative unified  
instruction and data level 2 (L2) cache with ECC  
– 36-bit real addressing  
– Master or slave support  
– Multiprocessing support features  
– Power and thermal management  
• MPX coherency module (MCM)  
• Address translation and mapping units (ATMUs)  
• DDR/DDR2 memory controller  
– 64- or 32-bit data path (72-bit with ECC)  
– Up to 533-MHz DDR2 data rate and up to 400 MHz  
DDR data rate  
• Dual integrated four-channel DMA controllers  
– All channels accessible by both local and remote masters  
– Supports transfers to or from any local memory or I/O  
port  
– Ability to start and flow control each DMA channel  
from external 3-pin interface  
• Watchdog timer  
• Dual global timer modules  
– Up to 16 Gbytes memory  
• 32-bit PCI interface, 33 or 66 MHz bus frequency  
• Dual PCI Express® controllers  
• Enhanced local bus controller (eLBC)  
– Operating at up to 133 MHz  
– PCI Express 1.0a compatible  
– Eight chip selects  
– PCI Express controller 1 supports x1, x2, and x4 link  
widths; PCI Express controller 2 supports x1, x2, x4, and  
x8 link widths  
• Display interface unit  
– Maximum display resolution: 1280 × 1024  
– Maximum display refresh rate: 60 Hz  
– Display color depth: up to 24 bpp  
– Display interface: parallel TTL  
• OpenPIC-compliant programmable interrupt controller  
(PIC)  
– 2.5 Gbaud, 2.0 Gbps lane  
• Device performance monitor  
– Supports eight 32-bit counters that count the occurrence  
of selected events  
– Ability to count up to 512 counter-specific events  
– Supports 64 reference events that can be counted on any  
of the 8 counters  
– Supports 16 programmable interrupt and processor task  
priority levels  
– Supports 12 discrete external interrupts and 48 internal  
interrupts  
– Eight global high resolution timers/counters that can  
generate interrupts  
– Supports duration and quantity threshold counting  
– Burstiness feature that permits counting of burst events  
with a programmable time between bursts  
– Triggering and chaining capability  
– Ability to generate an interrupt on overflow  
• IEEE Std 1149.1™ compliant, JTAG boundary scan  
• Available as 783-pin, flip-chip, plastic ball grid array  
(FC-PBGA)  
– Support for PCI Express message-shared interrupts  
(MSIs)  
2
• Dual I C controllers  
2
– Master or slave I C mode support  
© Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.  
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