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MC74VHC573ML2 PDF预览

MC74VHC573ML2

更新时间: 2024-11-30 21:11:55
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路
页数 文件大小 规格书
8页 203K
描述
IC,LATCH,SINGLE,8-BIT,AHC/VHC-CMOS,SOP,20PIN,PLASTIC

MC74VHC573ML2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP20,.3Reach Compliance Code:not_compliant
风险等级:5.92JESD-30 代码:R-PDSO-G20
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:D LATCH最大I(ol):0.008 A
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
电源:2/5.5 VProp。Delay @ Nom-Sup:10 ns
认证状态:Not Qualified子类别:FF/Latches
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

MC74VHC573ML2 数据手册

 浏览型号MC74VHC573ML2的Datasheet PDF文件第2页浏览型号MC74VHC573ML2的Datasheet PDF文件第3页浏览型号MC74VHC573ML2的Datasheet PDF文件第4页浏览型号MC74VHC573ML2的Datasheet PDF文件第5页浏览型号MC74VHC573ML2的Datasheet PDF文件第6页浏览型号MC74VHC573ML2的Datasheet PDF文件第7页 
The MC74VHC573 is an advanced high speed CMOS octal latch  
with 3–state output fabricated with silicon gate CMOS technology. It  
achieves high speed operation similar to equivalent Bipolar Schottky  
TTL while maintaining CMOS low power dissipation.  
http://onsemi.com  
This 8–bit D–type latch is controlled by a latch enable input and an  
output enable input. When the output enable input is high, the eight  
outputs are in a high impedance state.  
MARKING  
DIAGRAMS  
20  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7V, allowing the interface of 5V systems  
to 3V systems.  
SOIC–20 WIDE  
DW SUFFIX  
CASE 751D  
VHC573  
AWLYYWW  
20  
1
1
20  
High Speed: t  
= 4.5ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
VHC  
573  
ALYW  
TSSOP–20  
DT SUFFIX  
CASE 948E  
20  
CC  
A
High Noise Immunity: V  
= V  
= 28% V  
NIL CC  
NIH  
1
1
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2V to 5.5V Operating Range  
20  
1
SOIC EIAJ  
M SUFFIX  
CASE 967  
VHC573  
AWLYYWW  
20  
Low Noise: V  
= 1.2V (Max)  
OLP  
1
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 218 FETs or 54.5 Equivalent Gates  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
1
2
3
4
5
6
7
8
9
20  
V
CC  
OE  
D0  
D1  
D2  
2
3
4
19  
18  
17  
D0  
D1  
D2  
Q0  
Q1  
Q2  
19 Q0  
18 Q1  
17 Q2  
16 Q3  
15 Q4  
14 Q5  
13 Q6  
12 Q7  
5
6
16  
15  
NONINVERTING  
OUTPUTS  
DATA  
INPUTS  
D3  
D4  
Q3  
Q4  
D3  
D4  
D5  
D6  
D7  
7
8
9
14  
13  
12  
D5  
D6  
D7  
Q5  
Q6  
Q7  
11  
1
LE  
GND 10  
11  
LE  
OE  
ORDERING INFORMATION  
FUNCTION TABLE  
INPUTS  
Device  
Package  
Shipping  
OUTPUT  
Q
MC74VHC573DW  
SOIC–WIDE  
38 / Rail  
OE  
LE  
D
MC74VHC573DWR2  
MC74VHC573DT  
MC74VHC573DTR2  
MC74VHC573M  
SOIC–WIDE 1000 / Reel  
TSSOP–20 75 / Rail  
TSSOP–20 2500 / Reel  
SOIC EIAJ 40 / Rail  
L
L
L
H
H
L
H
L
X
X
H
L
No Change  
Z
H
X
MC74VHC573MEL  
SOIC EIAJ 2000 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
April, 2000 – Rev. 3  
MC74VHC573/D  

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