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MC74VHC393

更新时间： 2024-11-29 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 计数器
页数 文件大小 规格书
8页 176K
描述
Dual 4-Bit Binary Ripple Counter

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中文翻译

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MC74VHC393 数据手册

 浏览型号MC74VHC393的Datasheet PDF文件第2页浏览型号MC74VHC393的Datasheet PDF文件第3页浏览型号MC74VHC393的Datasheet PDF文件第4页浏览型号MC74VHC393的Datasheet PDF文件第5页浏览型号MC74VHC393的Datasheet PDF文件第6页浏览型号MC74VHC393的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC393 is an advanced high speed CMOS dual 4–bit binary  
ripple counter fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
This device consists of two independent 4–bit binary ripple counters with  
parallel outputs from each counter stage. A ÷256 counter can be obtained by  
cascading the two binary counters.  
D SUFFIX  
14–LEAD SOIC PACKAGE  
CASE 751A–03  
Internal flip–flops are triggered by high–to–low transitions of the clock  
input. Reset for the counters is asynchronous and active–high. State  
changes of the Q outputs do not occur simultaneously because of internal  
ripple delays. Therefore, decoded output signals are subject to decoding  
spikes and should not be used as clocks or as strobes except when gated  
with the Clock of the VHC393.  
DT SUFFIX  
14–LEAD TSSOP PACKAGE  
CASE 948G–01  
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems  
to 3V systems.  
•
•
•
•
•
•
•
•
•
•
•
High Speed: f  
= 170MHz (Typ) at V  
= 5V  
max  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2V to 5.5V Operating Range  
= V  
= 28% V  
NIL CC  
NIH  
M SUFFIX  
14–LEAD SOIC EIAJ PACKAGE  
CASE 965–01  
Low Noise: V  
= 0.8V (Max)  
OLP  
ORDERING INFORMATION  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 236 FETs or 59 Equivalent Gates  
MC74VHCXXXD  
MC74VHCXXXDT  
MC74VHCXXXM  
SOIC  
TSSOP  
SOIC EIAJ  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
CP1  
RD1  
1QA  
1QB  
1QC  
1QD  
1
2
3
4
14  
13  
12  
11  
V
CC  
CP2  
RD2  
2QA  
3, 11  
BINARY  
COUNTER  
nQA  
nQB  
nQC  
nQD  
4, 10  
5, 9  
1, 13  
2, 12  
CPn  
RDn  
6, 8  
5
6
10  
9
2QB  
2QC  
GND  
7
8
2QD  
FUNCTION TABLE  
Inputs  
Clock  
Reset  
Outputs  
X
H
L
↑
H
L
L
L
L
L
No Change  
No Change  
No Change  
Next State  
↓
6/97  
REV 0  
Motorola, Inc. 1997  
12345678

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MC74VHC393DT MOTOROLA

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MC74VHC393DTR2 MOTOROLA

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 		AHC/VHC SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, PLASTIC, TSS
MC74VHC393M ONSEMI

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MC74VHC393M MOTOROLA

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 		AHC/VHC SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, EIAJ, PLASTI
MC74VHC393MEL ONSEMI

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 		AHC/VHC/H/U/V SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, EIAJ,

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