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MC74VHC1GT86DFT4 PDF预览

MC74VHC1GT86DFT4

更新时间： 2024-01-02 06:32:47
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描述
2-Input Exclusive OR Gate / CMOS Logic Level Shifter with LSTTL?Compatible Inputs

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中文翻译

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MC74VHC1GT86DFT4 技术参数

生命周期：Contact Manufacturer包装说明：SC-70, 5 PIN
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.83系列：AHC/VHC/H/U/V
JESD-30 代码：R-PDSO-G5逻辑集成电路类型：XOR GATE
最大I（ol）：0.008 A功能数量：1
输入次数：2端子数量：5
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：TSSOP5/6,.08封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
电源：3.3/5 VProp。Delay @ Nom-Sup：12 ns
传播延迟（tpd）：19.5 ns认证状态：Not Qualified
施密特触发器：NO子类别：Gates
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL

MC74VHC1GT86DFT4 数据手册

 浏览型号MC74VHC1GT86DFT4的Datasheet PDF文件第2页浏览型号MC74VHC1GT86DFT4的Datasheet PDF文件第3页浏览型号MC74VHC1GT86DFT4的Datasheet PDF文件第4页 
2-Input Exclusive OR Gate / CMOS Logic Level Shifter  
with LSTTL–Compatible Inputs  
MC74VHC1GT86  
The MC74VHC1GT86 is an advanced high speed CMOS 2–input Exclusive OR gate fabricated with silicon gate CMOS technology.  
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.  
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.  
The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from  
3.0 V CMOS logic to 5.0V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power supply.  
The MC74VHC1GT86 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT86 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when  
V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,  
battery backup, hot insertion, etc.  
• High Speed: t PD = 4.8 ns (Typ) at V CC = 5 V  
• Power Down Protection Provided on Inputs and Outputs  
• Balanced Propagation Delays  
• Low Power Dissipation: I CC = 2 mA (Max) at T A = 25°C  
• TTL–Compatible Inputs: V IL = 0.8 V; V IH = 2.0 V  
• Pin and Function Compatible with Other Standard Logic Families  
• Chip Complexity: FETs = 83; Equivalent Gates = 16  
• CMOS–Compatible Outputs: V OH > 0.8 V CC  
V OL < 0.1 V CC @Load  
;
MARKING DIAGRAMS  
5
4
1
2
3
VMd  
SC–70/SC–88A/SOT–353  
DF SUFFIX  
CASE 419A  
Pin 1  
d = Date Code  
5
Figure 1. Pinout (Top View)  
4
VMd  
1
2
3
Figure 2. Logic Symbol  
SOT–23/TSOP–5/SC–59  
DT SUFFIX  
CASE 483  
Pin 1  
d = Date Code  
FUNCTION TABLE  
Inputs  
Output  
PIN ASSIGNMENT  
A
L
B
L
Y
L
1
2
3
4
5
IN B  
IN A  
L
H
L
H
H
L
GND  
OUT Y  
V CC  
H
H
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the  
package dimensions section on page 4 of this data sheet.  
VHT86–1/4  
1234

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