MC74VHC1G50,
MC74VHC1GT50
Buffer
The MC74VHC1G50 / MC74VHC1GT50 is an advanced high
speed CMOS buffer in tiny footprint packages. The MC74VHC1G50
has CMOS level input thresholds while the MC74VHC1GT50 has
TTL level input thresholds.
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The input structures provide protection when voltages up to 5.5 V
are applied, regardless of the supply voltage. This allows the device to
be used to interface 5 V circuits to 3 V circuits. The output structures
MARKING
DIAGRAMS
also provide protection when V = 0 V and when the output voltage
CC
SC−88A
DF SUFFIX
CASE 419A
exceeds V . These input and output structures help prevent device
XX MG
CC
G
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
SC−74A
DBV SUFFIX
CASE 318BQ
• Designed for 2.0 V to 5.5 V V Operation
CC
XXX MG
• 3.5 ns t at 5 V (typ)
PD
G
• Inputs/Outputs Over−Voltage Tolerant up to 5.5 V
• I
Supports Partial Power Down Protection
• Source/Sink 8 mA at 3.0 V
OFF
5
TSOP−5
DT SUFFIX
CASE 483
XX MG
5
• Available in SC−88A, SC−74A, TSOP−5, SOT−553, SOT−953 and
UDFN6 Packages
G
1
1
• Chip Complexity < 100 FETs
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
SOT−553
XV5 SUFFIX
CASE 463B
XX MG
G
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
SOT−953
P5 SUFFIX
CASE 527AE
X M
1
1
IN A
OUT Y
UDFN6
1.45 x 1.0
CASE 517AQ
XM
Figure 1. Logic Symbol
1
UDFN6
1.0 x 1.0
CASE 517BX
X M
1
XX
M
G
= Specific Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
November, 2018 − Rev. 13
MC74VHC1G50/D