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MC74VHC1G09DTT3 PDF预览

MC74VHC1G09DTT3

更新时间: 2024-01-08 01:37:59
品牌 Logo 应用领域
ETL
页数 文件大小 规格书
4页 576K
描述
2-Input AND Gate with Open Drain Output

MC74VHC1G09DTT3 技术参数

生命周期:Contact Manufacturer包装说明:SOP, TSOP5/6,.11,37
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.76系列:AHC/VHC/H/U/V
JESD-30 代码:R-PDSO-G5负载电容(CL):50 pF
逻辑集成电路类型:AND GATE最大I(ol):0.008 A
功能数量:1输入次数:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
电源:2/5.5 VProp。Delay @ Nom-Sup:11 ns
传播延迟(tpd):16.5 ns认证状态:Not Qualified
施密特触发器:NO子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUALBase Number Matches:1

MC74VHC1G09DTT3 数据手册

 浏览型号MC74VHC1G09DTT3的Datasheet PDF文件第2页浏览型号MC74VHC1G09DTT3的Datasheet PDF文件第3页浏览型号MC74VHC1G09DTT3的Datasheet PDF文件第4页 
2-Input AND Gate with  
Open Drain Output  
MC74VHC1G09  
The MC74VHC1G09 is an advanced high speed CMOS 2–input AND gate with open drain output fabricated with silicon gate CMOS  
technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.  
The internal circuit is composed of three stages, including an open drain output which provides the capability to set output switching  
level. This allows the MC74VHC1G09 to be used to interface 5 V circuits to circuits of any voltage between V CC and 7 V using an  
external resistor and power supply.  
The MC74VHC1G09 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage.  
• High Speed: t PD = 4.3 ns (Typ) at V CC = 5 V  
• Low Internal Power Dissipation: I CC = 2 mA (Max) at T A = 25°C  
• Power Down Protection Provided on Inputs  
• Pin and Function Compatible with Other Standard Logic Families  
• Chip Complexity: FETs = 62; Equivalent Gates = 16  
MARKING DIAGRAMS  
5
4
1
2
VXd  
3
SC–88A/SOT–353/SC–70  
DF SUFFIX  
CASE 419A  
Pin 1  
d = Date Code  
5
Figure 1. Pinout (Top View)  
4
VXd  
1
2
3
Figure 2. Logic Symbol  
TSOP–5/SOT–23/SC–59  
DT SUFFIX  
CASE 483  
Pin 1  
d = Date Code  
FUNCTION TABLE  
Inputs  
Output  
PIN ASSIGNMENT  
A
L
B
L
Y
L
L
L
Z
1
2
3
4
5
IN B  
IN A  
L
H
L
GND  
OUT Y  
V CC  
H
H
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the  
package dimensions section on page 4 of this data sheet.  
VH9–1/4  

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