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MC74VHC1G125DTT1G PDF预览

MC74VHC1G125DTT1G

更新时间: 2024-11-03 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 71K
描述
Noninverting 3-State Buffer

MC74VHC1G125DTT1G 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:TSOP包装说明:LEAD FREE, SC-59, SOT-23, TSOP-5
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.5
Is Samacsys:N控制类型:ENABLE LOW
系列:AHC/VHCJESD-30 代码:R-PDSO-G5
长度:3 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
位数:1功能数量:1
端口数量:2端子数量:5
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:2/5.5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):16 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
宽度:1.5 mmBase Number Matches:1

MC74VHC1G125DTT1G 数据手册

 浏览型号MC74VHC1G125DTT1G的Datasheet PDF文件第2页浏览型号MC74VHC1G125DTT1G的Datasheet PDF文件第3页浏览型号MC74VHC1G125DTT1G的Datasheet PDF文件第4页浏览型号MC74VHC1G125DTT1G的Datasheet PDF文件第5页浏览型号MC74VHC1G125DTT1G的Datasheet PDF文件第6页 
MC74VHC1G125  
Noninverting 3−State Buffer  
The MC74VHC1G125 is an advanced high speed CMOS  
noninverting 3−state buffer fabricated with silicon gate CMOS  
technology. It achieves high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining CMOS low power  
dissipation.  
The internal circuit is composed of three stages, including a buffered  
3−state output which provides high noise immunity and stable output.  
The MC74VHC1G125 input structure provides protection when  
voltages up to 7.0 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1G125 to be used to interface 5.0 V circuits to  
3.0 V circuits.  
http://onsemi.com  
MARKING  
DIAGRAMS  
SC−88A/SOT−353/SC−70  
DF SUFFIX  
W0d  
CASE 419A  
Features  
These are Pb−Free Devices  
Pin 1  
d = Date Code  
High Speed: t = 3.5 ns (Typ) at V = 5.0 V  
PD  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 58; Equivalent Gates = 15  
W0d  
TSOP−5/SOT−23/SC−59  
DT SUFFIX  
CASE 483  
Pin 1  
d = Date Code  
PIN ASSIGNMENT  
1
2
3
4
5
OE  
IN A  
1
2
3
5
V
CC  
OE  
IN A  
GND  
GND  
OUT Y  
V
CC  
4
OUT Y  
FUNCTION TABLE  
OE Input  
A Input  
Y Output  
L
H
X
L
L
L
H
Z
Figure 1. Pinout (Top View)  
H
ORDERING INFORMATION  
OE  
IN A  
EN  
OUT Y  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
September, 2004 − Rev. 12  
MC74VHC1G125/D  

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