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MC74HCXXXDW

更新时间： 2024-01-31 05:14:53
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摩托罗拉 - MOTOROLA 栅
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7页 226K
描述
High–Performance Silicon–Gate CMOS

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MC74HCXXXDW 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
The MC54/74HC563 is identical in pinout to the LS563. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
This device is identical in function to the HC533 but has the Data Inputs on  
the opposite side of the package from the outputs to facilitate PC board  
layout.  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. The data appears at the outputs  
in inverted form. When Latch Enable goes low, data meeting the setup and  
hold time becomes latched.  
The Output Enable input does not affect the state of the latches, but when  
Output Enable is high, all device outputs are forced to the high–impedance  
state. Thus, data may be latched even when the outputs are not enabled.  
The HC573 is the noninverting version of this function.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
ORDERING INFORMATION  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXDW SOIC  
Ceramic  
Plastic  
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
PIN ASSIGNMENT  
OUTPUT  
ENABLE  
1
20  
V
CC  
•
Chip Complexity: 202 FETs or 50.5 Equivalent Gates  
D0  
2
3
4
19  
18  
17  
Q0  
Q1  
Q2  
D1  
D2  
LOGIC DIAGRAM  
D3  
D4  
5
16  
15  
14  
13  
12  
11  
Q3  
Q4  
Q5  
Q6  
Q7  
19  
2
3
4
5
6
7
8
9
6
D0  
D1  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
18  
17  
16  
15  
14  
13  
12  
D5  
7
D6  
8
D2  
DATA  
INPUTS  
D3  
INVERTING  
OUTPUTS  
D7  
9
LATCH  
ENABLE  
D4  
GND  
10  
D5  
D6  
D7  
FUNCTION TABLE  
LATCH  
ENABLE  
11  
1
Inputs  
Output  
PIN 20 = V  
CC  
PIN 10 = GND  
OUTPUT  
ENABLE  
Output Latch  
Enable Enable  
D
Q
L
L
L
H
H
L
H
L
X
X
L
H
No Change  
Z
H
X
X = don’t care  
Z = high impedance  
10/95  
REV 6  
Motorola, Inc. 1995  
1234567

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与MC74HCXXXDW相关器件

型号 品牌 获取价格 描述 数据表
MC74HCXXXN MOTOROLA

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 		High–Performance Silicon–Gate CMOS
MC74HCXXXXAD MOTOROLA

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 		ANALOG MULTIPLEXERS/ DEMULTIPLEXERS
MC74HCXXXXAD FREESCALE

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 		Quad Analog Switch/Multiplexer/Demultiplexer
MC74HCXXXXADT FREESCALE

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 		Quad Analog Switch/Multiplexer/Demultiplexer
MC74HCXXXXADT MOTOROLA

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 		ANALOG MULTIPLEXERS/ DEMULTIPLEXERS
MC74HCXXXXADW MOTOROLA

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 		ANALOG MULTIPLEXERS/ DEMULTIPLEXERS
MC74HCXXXXAN MOTOROLA

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 		ANALOG MULTIPLEXERS/ DEMULTIPLEXERS
MC74HCXXXXAN FREESCALE

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 		Quad Analog Switch/Multiplexer/Demultiplexer
MC74HCXXXXD ONSEMI

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 		High-Performance Silicon-Gate CMOS
MC74HCXXXXD FREESCALE

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 		Analog Multiplexers/ Demultiplexers High-Performance Silicon-Gate CMOS

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