SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
20
The MC54/74HC533A is identical in pinout to the LS533. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The Data appears at the
outputs in inverted form. When Latch Enable goes low, data meeting the
setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high-impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC533A is identical in function to the HC563 but has the data inputs
on the opposite side of the package from the outputs to facilitate PC board
layout.
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
1
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
ORDERING INFORMATION
This device is similar in function to the HC373A, which has noninverting
outputs.
MC54HCXXXAJ
Ceramic
Plastic
SOIC
MC74HCXXXAN
MC74HCXXXADW
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
PIN ASSIGNMENT
OUTPUT
ENABLE
1
20
V
CC
•
Chip Complexity: 256 FETs or 64 Equivalent Gates
Q0
2
3
19
18
Q7
D7
D0
D1
4
17
D6
Q1
Q2
5
16
15
14
13
12
11
Q6
Q5
D5
D4
Q4
LOGIC DIAGRAM
6
D2
7
2
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
D3
8
5
6
4
Q3
9
7
LATCH
ENABLE
GND
10
8
9
DATA
INPUTS
INVERTING
OUTPUTS
13
14
17
18
12
15
16
19
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable
D
Q
L
L
L
H
H
L
H
L
X
X
L
H
No Change
Z
11
1
LATCH ENABLE
PIN 20 = V
CC
PIN 10 = GND
H
X
OUTPUT ENABLE
X = Don’t Care
Z = High Impedance
3/97
REV 3
1
Motorola, Inc. 1997