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MC74F1803 PDF预览

MC74F1803

更新时间: 2024-11-20 22:31:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟驱动器触发器
页数 文件大小 规格书
5页 82K
描述
CLOCK DRIVER QUAD D-TYPE FLIP-FLOP WITH MATCHED PROPAGATION DELAYS

MC74F1803 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74F1803 is a high–speed, low–power, quad D–type flip–flop  
featuringseparate D–type inputs and inverting outputs with closely matched  
propagation delays. With a buffered clock (CP) input that is common to all  
flip–flops, the MC74F1803 is useful in high–frequency systems as a clock  
driver, providing multiple outputs that are synchronous. Because of the  
matched propagation delays, the duty cycles of the output waveforms in a  
clock driver application are symmetrical within 2.0 nanoseconds.  
CLOCK DRIVER QUAD  
D–TYPE FLIP–FLOP WITH  
MATCHED PROPAGATION  
DELAYS  
Edge–Triggered D–Type Inputs  
Buffered Positive Edge–Triggered Clock  
Matched Outputs for Synchronous Clock Driver Applications  
Outputs Guaranteed for Simultaneous Switching  
N SUFFIX  
PLASTIC  
CASE 646–06  
14  
1
Pinout: 14–Lead Plastic (Top View)  
V
NC  
13  
O
D
D
O
2
CP  
8
D SUFFIX  
SOIC  
CASE 751A–03  
CC  
3
3
2
14  
12  
11  
10  
9
14  
1
LOGIC SYMBOL  
1
2
3
4
5
6
7
4
5
10  
11  
GND  
NC  
O
D
D
O
1
GND  
0
0
1
D0  
D1  
D2  
D3  
8
CP  
O0 O1 O2 O3  
LOGIC DIAGRAM  
D0  
D1  
D2  
D3  
3
6
9
12  
V
= PIN 14  
CC  
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
GND = PINS 1 AND 7  
NC = PINS 2 AND 13  
CP  
O
O
O
O
3
0
1
2
V
CC  
= Pin 14; GND = Pins 1,7; NC = Pins 2, 13  
NOTE: This diagram is provided only for the understanding of logic operations and  
should not be used to estimate propagation delays  
7/95  
REV 4  
1
Motorola, Inc. 1995  

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