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MC74ACT273MR2 PDF预览

MC74ACT273MR2

更新时间: 2024-11-11 15:41:03
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
7页 186K
描述
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, EIAJ, SO-20

MC74ACT273MR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:EIAJ, SO-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.64
系列:ACTJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.575 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:125000000 Hz最大I(ol):0.024 A
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):12 ns认证状态:Not Qualified
座面最大高度:2.05 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.275 mm最小 fmax:125 MHz
Base Number Matches:1

MC74ACT273MR2 数据手册

 浏览型号MC74ACT273MR2的Datasheet PDF文件第2页浏览型号MC74ACT273MR2的Datasheet PDF文件第3页浏览型号MC74ACT273MR2的Datasheet PDF文件第4页浏览型号MC74ACT273MR2的Datasheet PDF文件第5页浏览型号MC74ACT273MR2的Datasheet PDF文件第6页浏览型号MC74ACT273MR2的Datasheet PDF文件第7页 
OCTAL D FLIP-FLOP  
The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered Clock (CP) and Master  
Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.  
The register is fully edge-triggered. The state of each D input, one setup time  
before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-  
flop’s Q output.  
All outputs will be forced LOW independently of Clock or Data inputs by a LOW  
voltage level on the MR input. The device is useful for applications where the true  
output only is required and the Clock and Master Reset are common to all storage  
elements.  
Ideal Buffer for MOS Microprocessor or Memory  
Eight Edge-Triggered D Flip-Flops  
Buffered Common Clock  
Buffered, Asynchronous Master Reset  
See MC74AC377 for Clock Enable Version  
See MC74AC373 for Transparent Latch Version  
See MC74AC374 for 3-State Version  
Outputs Source/Sink 24 mA  
N SUFFIX  
CASE 738-03  
PLASTIC  
• ′ACT273 Has TTL Compatible Inputs  
DW SUFFIX  
CASE 751D-04  
PLASTIC  
V
Q
D
D
Q
Q
D
D
Q
4
CP  
11  
CC  
7
7
6
6
5
5
4
20  
19  
18  
17  
16  
15  
14  
12  
13  
LOGIC SYMBOL  
1
2
3
4
5
6
7
9
8
10  
D
CP  
D
Q
D
Q
D
Q
D
Q
D
D
Q
D
Q
0
1
2
3
4
5
6
7
MR  
Q
D
D
Q
Q
D
D
Q
3
GND  
0
0
1
1
2
2
3
MR  
Q
Q
5
0
1
2
3
4
6
7
PIN NAMES  
D –D  
0
Data Inputs  
Master Reset  
7
MR  
CP  
Q –Q  
0
Clock Pulse Input  
Data Outputs  
7
FACT DATA  
5-1  

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