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MC74ACT253ML2 PDF预览

MC74ACT253ML2

更新时间: 2024-11-15 14:53:15
品牌 Logo 应用领域
安森美 - ONSEMI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
8页 179K
描述
IC,LOGIC MUX,DUAL,4-INPUT,ACT-CMOS,SOP,16PIN,PLASTIC

MC74ACT253ML2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP16,.3Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.73
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.024 A功能数量:2
输入次数:4端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:5 V
Prop。Delay @ Nom-Sup:14.5 ns认证状态:Not Qualified
子类别:Multiplexer/Demultiplexers标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

MC74ACT253ML2 数据手册

 浏览型号MC74ACT253ML2的Datasheet PDF文件第2页浏览型号MC74ACT253ML2的Datasheet PDF文件第3页浏览型号MC74ACT253ML2的Datasheet PDF文件第4页浏览型号MC74ACT253ML2的Datasheet PDF文件第5页浏览型号MC74ACT253ML2的Datasheet PDF文件第6页浏览型号MC74ACT253ML2的Datasheet PDF文件第7页 
DUAL 4-INPUT  
MULTIPLEXER WITH  
3-STATE OUTPUTS  
The MC74AC253/74ACT253 is a dual 4-input multiplexer with 3-state outputs. It  
can select two bits of data from four sources using common select inputs. The  
outputs may be individually switched to a high impedance state with a HIGH on the  
respective Output Enable (OE) inputs, allowing the outputs to interface directly with  
bus oriented systems.  
Multifunctional Capability  
Noninverting 3-State Outputs  
Outputs Source/Sink 24 mA  
• ′ACT253 Has TTL Compatible Inputs  
N SUFFIX  
CASE 648-08  
PLASTIC  
V
OE  
S
I
I
I
I
Z
b
CC  
b
0
3b  
13  
2b  
12  
1b  
11  
0b  
10  
16  
15  
14  
9
PIN NAMES  
I
I
–I  
–I  
0b 3b  
Side A Data Inputs  
Side B Data Inputs  
Common Select Inputs  
Side A Output Enable Input  
Side B Output Enable Input  
3-State Outputs  
0a 3a  
D SUFFIX  
CASE 751B-05  
PLASTIC  
S , S  
OE  
OE  
0
1
a
b
1
2
3
4
5
6
7
8
Z
Z
OE  
S
1
I
I
I
I
0a  
Z
a
GND  
a,  
b
a
3a  
2a  
1a  
TRUTH TABLE  
Select  
Inputs  
Output  
Enable  
Data Inputs  
Outputs  
LOGIC SYMBOL  
S
0
S
1
I
0
I
1
I
2
I
3
OE  
Z
X
L
L
H
H
L
L
H
H
X
L
L
L
L
H
H
H
H
X
L
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
Z
L
H
L
H
L
H
L
OE  
0
I
I
I
I
I
I
I
I
OE  
a
0a 1a 2a 3a 0b 1b 2b 3b b  
S
S
H
X
X
X
X
X
X
1
Z
Z
b
a
H
H
Address inputs S and S are common to both sections.  
0
1
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
FACT DATA  
5-1  

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