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MC74AC256D

更新时间: 2024-11-21 22:46:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器双倍数据速率
页数 文件大小 规格书
7页 235K
描述
DUAL 4-BIT ADDRESSABLE LATCH

MC74AC256D 数据手册

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DUAL 4-BIT  
ADDRESSABLE  
LATCH  
The MC74AC256/74ACT256 dual addressable latch has four distinct modes  
of operation which are selectable by controlling the Clear and Enable inputs  
(see Function Table). In the addressable latch mode, data at the Data (D) inputs  
is written into the addressed latches. The addressed latches will follow the Data  
input with all unaddressed latches remaining in their previous states.  
In the memory mode, all latches remain in their previous states and are  
unaffected by the Data or Address inputs. To eliminate the possibility of entering  
erroneous data in the latches, the enable should be held HIGH (inactive) while  
the address lines are changing. In the dual 1-of-4 decoding or demultiplexing  
mode (MR = E = LOW), addressed outputs will follow the level of the D inputs  
with all other outputs LOW. In the clear mode, all outputs are LOW and unaffected  
by the Address and Data inputs.  
N SUFFIX  
CASE 648-08  
PLASTIC  
Combines Dual Demultiplexer and 8-Bit Latch  
Serial-to-Parallel Capability  
Output from Each Storage Bit Available  
Random (Addressable) Data Entry  
Easily Expandable  
Common Clear Input  
Useful as Dual 1-of-4 Active HIGH Decoder  
D SUFFIX  
CASE 751B-05  
PLASTIC  
V
MR  
15  
E
D
Q
Q
Q
Q
0b  
CC  
16  
b
3b  
12  
2b  
11  
1b  
10  
14  
13  
9
1
2
3
4
5
6
7
8
A
A
D
Q
Q
Q
Q
3a  
GND  
0
1
a
0a  
1a  
2a  
LOGIC SYMBOL  
D
D
b
a
A
A
Q
E
0
MR  
1
Q
Q
Q
Q
Q
Q
Q
0a 1a 2a 3a 0b 1b 2b 3b  
FACT DATA  
5-1  

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