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MC56603AGC60 PDF预览

MC56603AGC60

更新时间: 2024-10-16 14:53:11
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
97页 1067K
描述
24-BIT, 60MHz, OTHER DSP, PBGA144, PLASTIC, BGA-144

MC56603AGC60 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:144
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.75
Is Samacsys:N地址总线宽度:16
桶式移位器:YES边界扫描:YES
最大时钟频率:60 MHz外部数据总线宽度:24
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PBGA-B144长度:13 mm
低功率模式:YES端子数量:144
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压:3.3 V最小供电电压:2.7 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:13 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

MC56603AGC60 数据手册

 浏览型号MC56603AGC60的Datasheet PDF文件第2页浏览型号MC56603AGC60的Datasheet PDF文件第3页浏览型号MC56603AGC60的Datasheet PDF文件第4页浏览型号MC56603AGC60的Datasheet PDF文件第5页浏览型号MC56603AGC60的Datasheet PDF文件第6页浏览型号MC56603AGC60的Datasheet PDF文件第7页 
Order this document by:  
DSP56603A/D  
Freescale Semiconductor, Inc.  
MOTOROLA  
SEMICONDUCTOR TECHNICAL DATA  
Rev. 0, 09/98  
DSP56603A  
16-BIT DIGITAL SIGNAL PROCESSOR  
The DSP56603A is a 16-bit fixed-point CMOS Digital Signal Processor (DSP) that is optimized for  
processing-intensive, yet cost-effective, low power consumption digital mobile communications  
applications. The DSP56603A is a member of the DSP56600 core family of DSPs, and is capable of  
executing one instruction per clock cycle.  
Figure 1 provides a block diagram of the DSP56603A, showing the core structures and the  
expansion areas. The DSP56600 core includes the Data Arithmetic Logic Unit (Data ALU),  
Address Generation Unit (AGU), Program Controller, Program Patch Detector, Bus Interface  
Unit, On-Chip Emulation (OnCEª) module, JTAG port, and a PhaseÐLocked Loop (PLL)-based  
clock generator. The expansion areas provide the program and data memories, as well as a  
versatile set of on-chip peripherals and external ports.  
3
16  
6
6
Memory Expansion Area  
Triple Dedicated  
Host  
Program  
Y Data  
SSI  
Interface  
or GPIO  
Pins  
X Data  
Memory  
RAM:  
8 K ´ 16  
5.5 K ´ 16  
10.5 K ´ 16  
Timer or  
GPIO  
Pins  
GPIO  
Pins  
Interface  
HI08 or  
GPIO  
Memory  
RAM:  
Memory  
RAM:  
16.5 K ´ 24  
8 K ´ 16 Switch Mode 0  
8 K ´ 16 Switch Mode 1  
10.5 K ´ 16 Switch Mode 2  
Pins  
19 K ´ 24  
11.5 K ´ 24  
ROM:  
3 K ´ 24  
Peripheral  
Expansion Area  
YAB  
XAB  
PAB  
Address  
Generation  
Unit  
16  
Address  
4
External  
Bus  
Interface  
16-bit  
DSP56600  
Core  
Program  
Patch  
Detector  
Control  
24  
YDB  
XDB  
PDB  
Data  
Internal  
Data  
Bus  
Switch  
Power  
Manage-  
ment  
EXTAL  
PCAP  
Clock  
Generator  
Data ALU  
Program  
Program  
Decode  
Controller  
Program  
Address  
Generator  
5
+
16 ´ 16 40 ® 40-bit MAC  
Two 40-bit Accumulators  
40-bit Barrel Shifter  
Interrupt  
JTAG  
Controller  
PLL  
OnCEª  
DE  
CLKOUT  
MODA/IRQA  
MODB/IRQB  
PINIT/NMI  
MODC/IRQC  
AA1259  
RESET  
MODD/IRQD  
Figure 1 DSP56603A Block Diagram  
© MOTOROLA, INC. 1998  
For More Information On This Product,  
Go to: www.freescale.com  
 

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