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MC33972APEK PDF预览

MC33972APEK

更新时间: 2024-11-12 14:59:31
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
32页 795K
描述
Switch Detection Interface, 22-switches with Suppressed Wakeup, 3.3 V / 5.0 V SPI , SOIC 32

MC33972APEK 数据手册

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Document Number: MC33972  
Rev. 19.0, 3/2012  
escale Semiconductor  
Technical Data  
Multiple Switch Detection  
Interface with Suppressed  
Wake-up  
33972/A/T  
MULTIPLE SWITCH  
DETECTION INTERFACE  
The 33972 Multiple Switch Detection Interface with suppressed  
wake-up is designed to detect the closing and opening of up to 22  
switch contacts. The switch status, either open or closed, is transferred  
to the microprocessor unit (MCU) through a serial peripheral interface  
(SPI). The device also features a 22-to-1 analog multiplexer for reading  
inputs as analog. The analog input signal is buffered and provided on  
the AMUX output pin for the MCU to read.  
The 33972 device has two modes of operation, Normal and Sleep.  
Normal mode allows programming of the device and supplies switch  
contacts with pull-up or pull-down current as it monitors switch change  
of state. The Sleep mode provides low quiescent current, which makes  
the 33972 ideal for automotive and industrial products requiring low  
sleep-state currents.  
EW SUFFIX (Pb-FREE)  
EK SUFFIX (Pb-FREE)  
98ASA10556D  
32-PIN SOICW EP  
98ARH99137A  
32-PIN SOICW  
ORDERING INFORMATION  
Features  
Temperature  
• Designed to operate 5.5 V VPWR 26 V  
Device  
Package  
Range (T )  
A
• Switch input voltage range -14 V to VPWR, 40 V Max  
• Interfaces directly to MPU using 3.3 V/5.0 V SPI protocol  
• Selectable wake-up on change of state  
• Selectable wetting current (16 or 2.0 mA)  
• 8 programmable inputs (switches to battery or ground)  
• 14 switch-to-ground inputs  
MC33972TEW/R2  
MC33972ATEW/R2  
MC33972ATEK/R2  
32 SOICW  
-40 °C to 125 °C  
32 SOICW EP  
• Typical standby current - VPWR = 100 μA and VDD = 20 μA  
• Active interrupt (INT) on change-of-switch state  
VDD  
POWER SUPPLY  
VBAT  
VBAT  
LVI  
33972  
SP0  
SP1  
VPWR  
VDD  
VBAT  
ENABLE  
VDD  
SP7  
WAKE  
SG0  
SG1  
MCU  
SI  
SCLK  
CS  
SO  
INT  
MOSI  
WATCHDOG  
RESET  
SCLK  
CS  
MISO  
INT  
SG12  
SG13  
AMUX  
AN0  
GND  
Figure 1. 33972 Simplified Application Diagram  
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,  
as may be required, to permit improvements in the design of its products.  
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.  

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