MC14490
Hex Contact Bounce
Eliminator
The MC14490 is constructed with complementary MOS enhancement
mode devices, and is used for the elimination of extraneous level changes
that result when interfacing with mechanical contacts. The digital contact
bounce eliminator circuit takes an input signal from a bouncing contact
and generates a clean digital signal four clock periods after the input has
stabilized. The bounce eliminator circuit will remove bounce on both the
“make” and the “break” of a contact closure. The clock for operation of
the MC14490 is derived from an internal R−C oscillator which requires
only an external capacitor to adjust for the desired operating frequency
(bounce delay). The clock may also be driven from an external clock
source or the oscillator of another MC14490 (see Figure 5).
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP−16
MC14490P
NOTE: Immediately after powerup, the outputs of the MC14490 are in
indeterminate states.
P SUFFIX
CASE 648
AWLYYWWG
1
Features
1
• Diode Protection on All Inputs
16
• Six Debouncers Per Package
• Internal Pullups on All Data Inputs
SOIC−16
DW SUFFIX
CASE 751G
14490
AWLYYWWG
• Can Be Used as a Digital Integrator, System Synchronizer, or Delay Line
• Internal Oscillator (R−C), or External Clock Source
• TTL Compatible Data Inputs/Outputs
1
1
• Single Line Input, Debounces Both “Make” and “Break” Contacts
• Does Not Require “Form C” (Single Pole Double Throw) Input Signal
• Cascadable for Longer Time Delays
• Schmitt Trigger on Clock Input (Pin 7)
• Supply Voltage Range = 3.0 V to 18 V
• Chip Complexity: 546 FETs or 136.5 Equivalent Gates
• Pb−Free Packages are Available*
16
SOEIAJ−16
MC14490
ALYWG
F SUFFIX
CASE 966
1
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Parameter
Symbol
Value
Unit
V
DC Supply Voltage Range
V
−0.5 to +18.0
G
= Pb−Free Package
DD
Input or Output Voltage Range
(DC or Transient)
V , V
in out
−0.5 to V
+ 0.5
V
DD
ORDERING INFORMATION
Input Current (DC or Transient) per Pin
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
I
10
mA
mW
°C
in
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
P
T
500
D
−55 to +125
−65 to +150
260
A
Storage Temperature Range
T
stg
°C
Lead Temperature (8−Second Soldering)
T
°C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 7
MC14490/D