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MC14490FR1 PDF预览

MC14490FR1

更新时间： 2024-11-23 21:19:15
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路
页数 文件大小 规格书
11页 161K
描述
SPECIALTY LOGIC CIRCUIT, PDSO16, EIAJ, SOP-16

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MC14490FR1 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOIC-16
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.66
计数方向：RIGHT系列：4000/14000/40000
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：10.2 mm逻辑集成电路类型：LOGIC CIRCUIT
位数：4功能数量：6
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 V传播延迟（tpd）：740 ns
认证状态：Not Qualified座面最大高度：2.05 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.275 mm最小 fmax：4.5 MHz
Base Number Matches：1

MC14490FR1 数据手册

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MC14490  
Hex Contact Bounce  
Eliminator  
The MC14490 is constructed with complementary MOS enhancement  
mode devices, and is used for the elimination of extraneous level changes  
that result when interfacing with mechanical contacts. The digital contact  
bounce eliminator circuit takes an input signal from a bouncing contact  
and generates a clean digital signal four clock periods after the input has  
stabilized. The bounce eliminator circuit will remove bounce on both the  
“make” and the “break” of a contact closure. The clock for operation of  
the MC14490 is derived from an internal R−C oscillator which requires  
only an external capacitor to adjust for the desired operating frequency  
(bounce delay). The clock may also be driven from an external clock  
source or the oscillator of another MC14490 (see Figure 5).  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP−16  
MC14490P  
P SUFFIX  
CASE 648  
AWLYYWWG  
NOTE: Immediately after powerup, the outputs of the MC14490 are in  
indeterminate states.  
1
1
16  
Features  
SOIC−16  
DW SUFFIX  
CASE 751G  
• Diode Protection on All Inputs  
14490  
AWLYYWWG  
• Six Debouncers Per Package  
• Internal Pullups on All Data Inputs  
1
1
1
• Can Be Used as a Digital Integrator, System Synchronizer, or Delay Line  
• Internal Oscillator (R−C), or External Clock Source  
• TTL Compatible Data Inputs/Outputs  
16  
SOEIAJ−16  
MC14490  
ALYWG  
F SUFFIX  
CASE 966  
1
• Single Line Input, Debounces Both “Make” and “Break” Contacts  
• Does Not Require “Form C” (Single Pole Double Throw) Input Signal  
• Cascadable for Longer Time Delays  
A
= Assembly Location  
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
• Schmitt Trigger on Clock Input (Pin 7)  
• Supply Voltage Range = 3.0 V to 18 V  
G
= Pb−Free Package  
• Chip Complexity: 546 FETs or 136.5 Equivalent Gates  
• These Devices are Pb−Free and are RoHS Compliant  
ORDERING INFORMATION  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
MAXIMUM RATINGS (Voltages Referenced to V  
Parameter  
)
SS  
Symbol  
Value  
Unit  
V
DC Supply Voltage Range  
V
DD  
−0.5 to +18.0  
Input or Output Voltage Range  
(DC or Transient)  
V , V  
in out  
−0.5 to V  
V
DD  
+ 0.5  
Input Current (DC or Transient) per Pin  
Power Dissipation, per Package (Note 1)  
Ambient Temperature Range  
I
10  
mA  
mW  
°C  
in  
P
500  
D
T
−55 to +125  
−65 to +150  
260  
A
Storage Temperature Range  
T
stg  
°C  
Lead Temperature (8−Second Soldering)  
T
°C  
L
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be  
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V and V  
in  
out  
should be constrained to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
May, 2013 − Rev. 10  
MC14490/D  
 
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与MC14490FR1相关器件

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MC14490L MOTOROLA

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 		Hex Contact Bounce Eliminator
MC14490LD MOTOROLA

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 		Logic Circuit, CMOS, CDIP16
MC14490LDS MOTOROLA

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 		Logic Circuit, CMOS, CDIP16
MC14490P ONSEMI

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 		Hex Contact Bounce Eliminator
MC14490P MOTOROLA

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 		Hex Contact Bounce Eliminator
MC14490PD MOTOROLA

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 		Logic Circuit, CMOS, PDIP16
MC14490PDS MOTOROLA

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 		Logic Circuit, CMOS, PDIP16
MC14490PG ONSEMI

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 		Hex Contact Bounce Eliminator
MC14490PS MOTOROLA

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 		Logic Circuit, CMOS, PDIP16
MC14490VL MOTOROLA

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 		Logic Circuit, CMOS, CDIP16

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