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MC14490FG PDF预览

MC14490FG

更新时间： 2024-10-02 04:41:03
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
11页 126K
描述
Hex Contact Bounce Eliminator

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中文翻译

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MC14490FG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP16,.3针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：8.46计数方向：RIGHT
系列：4000/14000/40000JESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：10.2 mm
逻辑集成电路类型：LOGIC CIRCUIT湿度敏感等级：3
位数：4功能数量：6
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5/15 V传播延迟（tpd）：740 ns
认证状态：Not Qualified座面最大高度：2.05 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：5.275 mm最小 fmax：4.5 MHz
Base Number Matches：1

MC14490FG 数据手册

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MC14490  
Hex Contact Bounce  
Eliminator  
The MC14490 is constructed with complementary MOS enhancement  
mode devices, and is used for the elimination of extraneous level changes  
that result when interfacing with mechanical contacts. The digital contact  
bounce eliminator circuit takes an input signal from a bouncing contact  
and generates a clean digital signal four clock periods after the input has  
stabilized. The bounce eliminator circuit will remove bounce on both the  
“make” and the “break” of a contact closure. The clock for operation of  
the MC14490 is derived from an internal R−C oscillator which requires  
only an external capacitor to adjust for the desired operating frequency  
(bounce delay). The clock may also be driven from an external clock  
source or the oscillator of another MC14490 (see Figure 5).  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP−16  
MC14490P  
NOTE: Immediately after powerup, the outputs of the MC14490 are in  
indeterminate states.  
P SUFFIX  
CASE 648  
AWLYYWWG  
1
Features  
1
• Diode Protection on All Inputs  
16  
• Six Debouncers Per Package  
• Internal Pullups on All Data Inputs  
SOIC−16  
DW SUFFIX  
CASE 751G  
14490  
AWLYYWWG  
• Can Be Used as a Digital Integrator, System Synchronizer, or Delay Line  
• Internal Oscillator (R−C), or External Clock Source  
• TTL Compatible Data Inputs/Outputs  
1
1
• Single Line Input, Debounces Both “Make” and “Break” Contacts  
• Does Not Require “Form C” (Single Pole Double Throw) Input Signal  
• Cascadable for Longer Time Delays  
• Schmitt Trigger on Clock Input (Pin 7)  
• Supply Voltage Range = 3.0 V to 18 V  
• Chip Complexity: 546 FETs or 136.5 Equivalent Gates  
• Pb−Free Packages are Available*  
16  
SOEIAJ−16  
MC14490  
ALYWG  
F SUFFIX  
CASE 966  
1
1
A
= Assembly Location  
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Parameter  
Symbol  
Value  
Unit  
V
DC Supply Voltage Range  
V
−0.5 to +18.0  
G
= Pb−Free Package  
DD  
Input or Output Voltage Range  
(DC or Transient)  
V , V  
in out  
−0.5 to V  
+ 0.5  
V
DD  
ORDERING INFORMATION  
Input Current (DC or Transient) per Pin  
Power Dissipation, per Package (Note 1)  
Ambient Temperature Range  
I
10  
mA  
mW  
°C  
in  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
P
T
500  
D
−55 to +125  
−65 to +150  
260  
A
Storage Temperature Range  
T
stg  
°C  
Lead Temperature (8−Second Soldering)  
T
°C  
L
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating: Plastic “P and D/DW”  
Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 − Rev. 7  
MC14490/D  
 
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中文翻译

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MC14490FG 替代型号

型号 品牌 替代类型 描述 数据表
MC14490FELG ONSEMI

完全替代

 Hex Contact Bounce Eliminator
MC14490DWR2G ONSEMI

完全替代

 Hex Contact Bounce Eliminator
MC14490DWG ONSEMI

完全替代

 Hex Contact Bounce Eliminator

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