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MC14024BCLDS PDF预览

MC14024BCLDS

更新时间: 2024-11-30 12:58:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
7页 214K
描述
4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 7-BIT UP BINARY COUNTER, CDIP14, 632-08

MC14024BCLDS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.11
计数方向:UP系列:4000/14000/40000
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
长度:19.495 mm负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
工作模式:ASYNCHRONOUS位数:7
功能数量:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 V传播延迟(tpd):2000 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
最小 fmax:1 MHzBase Number Matches:1

MC14024BCLDS 数据手册

 浏览型号MC14024BCLDS的Datasheet PDF文件第2页浏览型号MC14024BCLDS的Datasheet PDF文件第3页浏览型号MC14024BCLDS的Datasheet PDF文件第4页浏览型号MC14024BCLDS的Datasheet PDF文件第5页浏览型号MC14024BCLDS的Datasheet PDF文件第6页浏览型号MC14024BCLDS的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 632  
The MC14024B is a 7–stage ripple counter with short propagation delays  
and high maximum clock rates. The Reset input has standard noise  
immunity, however the Clock input has increased noise immunity due to  
Hysteresis. The output of each counter stage is buffered.  
Diode Protection on All Inputs  
Output Transitions Occur on the Falling Edge of the Clock Pulse  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
Pin–for–Pin Replacement for CD4024B  
P SUFFIX  
PLASTIC  
CASE 646  
D SUFFIX  
SOIC  
CASE 751A  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
V
DD  
– 0.5 to + 18.0  
V , V  
in out  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
l , l  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
T
A
= – 55° to 125°C for all packages.  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
T
stg  
– 65 to + 150  
260  
PIN ASSIGNMENT  
T
Lead Temperature (8–Second Soldering)  
C
L
CLOCK  
RESET  
Q7  
1
2
3
4
5
6
14  
13  
12  
11  
10  
9
V
DD  
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
NC  
Q1  
Q2  
NC  
Q3  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
Q6  
Q5  
LOGIC DIAGRAM  
Q4  
V
7
8
NC  
SS  
1
CLOCK  
RESET  
C
Q
C
Q
C
R
Q
Q
C
R
Q
Q
V
V
= PIN 14  
DD  
= PIN 7  
SS  
NC = NO CONNECTION  
R
Q
R
Q
2
12  
11  
4
3
Q1  
Q2  
Q6  
Q7  
Q3 = PIN 9  
Q4 = PIN 6  
Q5 = PIN 5  
REV 3  
1/94  
Motorola, Inc. 1995  

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