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MC14025BALD PDF预览

MC14025BALD

更新时间: 2024-11-23 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA
页数 文件大小 规格书
11页 330K
描述
4000/14000/40000 SERIES, TRIPLE 3-INPUT NOR GATE, CDIP14, 632-08

MC14025BALD 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.41Is Samacsys:N
系列:4000/14000/40000JESD-30 代码:R-GDIP-T14
JESD-609代码:e0长度:19.495 mm
负载电容(CL):50 pF逻辑集成电路类型:NOR GATE
功能数量:3输入次数:3
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
传播延迟(tpd):300 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC14025BALD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The B Series logic gates are constructed with P and N channel  
enhancement mode devices in a single monolithic structure (Complemen-  
tary MOS). Their primary use is where low power dissipation and/or high  
noise immunity is desired.  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
All Outputs Buffered  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range.  
Double Diode Protection on All Inputs Except: Triple Diode Protection  
on MC14011B and MC14081B  
Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix  
Devices (Exceptions: MC14068B and MC14078B)  
L SUFFIX  
CERAMIC  
CASE 632  
P SUFFIX  
PLASTIC  
CASE 646  
D SUFFIX  
SOIC  
CASE 751A  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
T
A
= – 55° to 125°C for all packages.  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
DD  
– 0.5 to + 18.0  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
l , l  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
T
stg  
– 65 to + 150  
260  
T
Lead Temperature (8–Second Soldering)  
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
This device contains protection circuitry to guard against damage  
due to high static voltages or electric fields. However, precautions must  
be taken to avoid applications of any voltage higher than maximum rated  
voltages to this high-impedance circuit. For proper operation, V and  
in  
V
out  
should be constrained to the range V  
SS  
(V or V ) V .  
in out DD  
Unused inputs must always be tied to an appropriate logic voltage  
level (e.g., either V or V ). Unused outputs must be left open.  
SS DD  
REV 3  
1/94  
Motorola, Inc. 1995  

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