MC10H211
Dual 3−Input 3−Output NOR
Gate
Description
The MC10H211 is designed to drive up to six transmission lines
simultaneously. The multiple outputs of this device also allow the wire
ORing of several levels of gating for minimization of gate and package
count.
The ability to control three parallel lines with minimum propagation
delay from a single point makes the MC10H211 particularly useful in
clock distribution applications where minimum clock skew is desired.
http://onsemi.com
MARKING DIAGRAMS*
16
1
Features
• Propagation Delay, 1.0 ns Typical
• Power Dissipation, 160 mW Typical
• Improved Noise Margin 150 mV
(Over Operating Voltage and Temperature Range)
• Voltage Compensated
MC10H211L
AWLYYWW
CDIP−16
L SUFFIX
CASE 620A
16
1
• MECL 10K™ Compatible
• Pb−Free Packages are Available*
MC10H211P
AWLYYWWG
16
1
2
3
4
PDIP−16
P SUFFIX
CASE 648
5
6
7
12
13
14
10H211
ALYWG
9
10
11
V
V
V
= PINS 1, 15
= PIN 16
CC1
CC2
SOEIAJ−16
CASE 966
= PIN 8
EE
Figure 1. Logic Diagram
1 20
V
A
V
V
B
B
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
CC2
CC1
OUT
OUT
OUT
10H211G
AWLYYWW
20
OUT
OUT
OUT
1
A
A
PLLC−20
FN SUFFIX
CASE 775
A
IN
A
B
B
B
IN
IN
IN
IN
A
= Assembly Location
= Year
A
IN
WL, L = Wafer Lot
YY, Y
V
EE
WW, W = Work Week
= Pb−Free Package
G
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
Figure 2. Dip Pin Assignment
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 9
MC10H211/D