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MC10162P PDF预览

MC10162P

更新时间: 2024-11-07 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI 解码器驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 91K
描述
Binary to 1-8 Decoder (High)

MC10162P 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.65Is Samacsys:N
系列:10K输入调节:STANDARD
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:19.175 mm逻辑集成电路类型:OTHER DECODER/DRIVER
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
输出特性:OPEN-EMITTER输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:-5.2 V最大电源电流(ICC):84 mA
Prop。Delay @ Nom-Sup:6.4 ns传播延迟(tpd):6 ns
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:Decoder/Drivers表面贴装:NO
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MC10162P 数据手册

 浏览型号MC10162P的Datasheet PDF文件第2页浏览型号MC10162P的Datasheet PDF文件第3页浏览型号MC10162P的Datasheet PDF文件第4页 
MC10162  
Binary to 1-8 Decoder  
(High)  
The MC10162 is designed to convert three lines of input data to a  
one–of–eight output. The selected output will be high while all other  
outputs are low. The enable inputs, when either or both are high, force  
all outputs low.  
http://onsemi.com  
The MC10162 is a true parallel decoder. No series gating is used  
internally, eliminating unequal delay times found in other decoders.  
This device is ideally suited for demultiplexer applications. One of  
the two enable inputs is used as the data input, while the other is used  
as a data enable input.  
MARKING  
DIAGRAMS  
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10162L  
AWLYYWW  
A complete mux/demux operation on 16 bits for data distribution is  
illustrated in Figure 1 of the MC10161 data sheet.  
1
P = 315 ns typ/pkg (No Load)  
16  
D
PDIP–16  
P SUFFIX  
CASE 648  
t = 4.0 ns typ  
pd  
MC10162P  
AWLYYWW  
t , t = 2.0 ns typ (20%–80%)  
r
f
1
LOGIC DIAGRAM  
1
E0Ą2  
E1Ą15  
PLCC–20  
FN SUFFIX  
CASE 775  
6ĄQ0  
5ĄQ1  
10162  
AWLYYWW  
4ĄQ2  
3ĄQ3  
13ĄQ4  
AĄ7  
BĄ9  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
12ĄQ5  
DIP PIN ASSIGNMENT  
11ĄQ6  
10ĄQ7  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
V
CC2  
CĄ14  
CC1  
E0  
E1  
C
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
Q3  
Q2  
Q1  
Q0  
A
CC2  
V
EE  
Q4  
Q5  
TRUTH TABLE  
Q6  
INPUTS  
OUTPUTS  
Q7  
B
E0  
E1  
C
B
A
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
V
EE  
L
H
H
L
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables  
on page 18 of the ON Semiconductor MECL Data Book  
(DL122/D).  
L
H
L
H
H
H
H
X
X
L
H
L
H
H
X
X
H
X
X
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10162L  
CDIP–16  
25 Units / Rail  
MC10162P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
MC10162FN  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10162/D  

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