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MC00LVELT22MNR4G PDF预览

MC00LVELT22MNR4G

更新时间: 2024-11-01 03:50:07
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
7页 80K
描述
3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator

MC00LVELT22MNR4G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DFN包装说明:LEAD FREE, DFN-8
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84最大延迟:0.6 ns
接口集成电路类型:TTL/CMOS TO PECL TRANSLATORJESD-30 代码:S-PDSO-G8
JESD-609代码:e4长度:2 mm
湿度敏感等级:1位数:1
功能数量:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:OPEN-EMITTER输出锁存器或寄存器:NONE
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:VSSOP封装等效代码:SOLCC8,.08,20
封装形状:SQUARE封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Level Translators最大供电电压:3.8 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:2 mmBase Number Matches:1

MC00LVELT22MNR4G 数据手册

 浏览型号MC00LVELT22MNR4G的Datasheet PDF文件第2页浏览型号MC00LVELT22MNR4G的Datasheet PDF文件第3页浏览型号MC00LVELT22MNR4G的Datasheet PDF文件第4页浏览型号MC00LVELT22MNR4G的Datasheet PDF文件第5页浏览型号MC00LVELT22MNR4G的Datasheet PDF文件第6页浏览型号MC00LVELT22MNR4G的Datasheet PDF文件第7页 
MC100LVELT22  
3.3VꢀDual LVTTL/LVCMOS  
to Differential LVPECL  
Translator  
Description  
http://onsemi.com  
MARKING  
The MC100LVELT22 is a dual LVTTL/LVCMOS to differential  
LVPECL translator. Because LVPECL (Low Voltage Positive ECL)  
levels are used, only +3.3 V and ground are required. The small outline  
8-lead package and the low skew, dual gate design of the LVELT22  
makes it ideal for applications which require the translation of a clock  
and a data signal.  
DIAGRAMS*  
8
8
1
KVT22  
ALYW  
G
Features  
SOIC−8  
D SUFFIX  
CASE 751  
350 ps Typical Propagation Delay  
<100 ps Output−to−Output Skew  
Flow Through Pinouts  
1
8
8
The 100 Series Contains Temperature Compensation  
1
KR22  
LVPECL Operating Range: V = 3.0 V to 3.8 V  
CC  
ALYWG  
TSSOP−8  
DT SUFFIX  
CASE 948R  
with GND = 0 V  
G
When Unused TTL Input is left Open, Q Output will Default High  
Pb−Free Packages are Available  
1
DFN8  
MN SUFFIX  
CASE 506AA  
1
4
A
L
Y
= Assembly Location  
= Wafer Lot  
= Year  
W = Work Week  
M = Date Code  
G
= Pb−Free Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
March, 2007 − Rev. 5  
MC100LVELT22/D  

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