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MC-454CA726LFA-A80 PDF预览

MC-454CA726LFA-A80

更新时间: 2024-11-25 19:42:43
品牌 Logo 应用领域
日电电子 - NEC 动态存储器内存集成电路
页数 文件大小 规格书
16页 162K
描述
Synchronous DRAM Module, 4MX72, 6ns, MOS, DIMM-168

MC-454CA726LFA-A80 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:,针数:168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.28风险等级:5.84
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
JESD-30 代码:R-XDMA-N168内存密度:301989888 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:168字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX72封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
认证状态:Not Qualified最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:MOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子位置:DUALBase Number Matches:1

MC-454CA726LFA-A80 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-454CA726  
4M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE  
UNBUFFERED TYPE  
Description  
The MC-454CA726 is a 4,194,304 words by 72 bits synchronous dynamic RAM module on which 5 pieces of 64M  
SDRAM : µPD4564163 are assembled.  
This module provides high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
4,194,304 words by 72 bits organization  
Clock frequency and access time from CLK  
Part number  
/CAS latency  
Clock frequency  
(MAX.)  
Access time from CLK  
Power consumption (MAX.)  
(MAX.)  
6 ns  
6 ns  
6 ns  
7 ns  
6 ns  
6 ns  
6 ns  
7 ns  
Active  
Standby  
9.0 mW  
MC-454CA726F-A80  
MC-454CA726F-A10  
MC-454CA726LFA-A80  
MC-454CA726LFA-A10  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
125 MHz  
100 MHz  
100 MHz  
77 MHz  
3,510 mW  
2,970 mW  
2,970 mW  
2,340 mW  
3,510 mW  
2,970 mW  
2,970 mW  
2,340 mW  
(CMOS level input )  
125 MHz  
100 MHz  
100 MHz  
77 MHz  
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Pulsed interface  
Possible to assert random column address in every cycle  
Quad internal banks controlled by BA0 and BA1 (Bank Select)  
Programmable burst-length : 1, 2, 4, 8 and full page  
Programmable wrap sequence (sequential / interleave)  
Programmable /CAS latency (2, 3)  
Automatic precharge and controlled precharge  
CBR (Auto) refresh and self refresh  
All DQs have 10 Ω ± 10 % of series resistor  
Single 3.3 V ± 0.3 V power supply  
LVTTL compatible  
4,096 refresh cycles / 64 ms  
Burst termination by Burst Stop command and Precharge command  
168-pin dual in-line memory module (Pin pitch = 1.27 mm)  
Unbuffered type  
Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. M13500EJ3V0DS00 (3rd edition)  
Date Published February 1999 NS CP (K)  
Printed in Japan  
The mark shows major revised points.  
1998  
©

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