MB9B320M Series
32-bit Arm® Cortex®-M3
FM3 Microcontroller
The MB9B320M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the Arm® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
such as various timers, ADCs, DACs and Communication Interfaces (USB, UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE9 product categories in “FM3 Family Peripheral Manual”.
Features
[USB device]
32-bit Arm® Cortex®-M3 Core
USB2.0 Full-Speed supported
Processor version: r2p1
Max 6 EndPoint supported
EndPoint 0 is control transfer
Up to 72 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or
Isochronous-transfer
EndPoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
EndPoint 1 to 5 are comprised of Double Buffers.
The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5: 64bytes
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
• Endpoint 1: 256bytes
[USB host]
Dual operation Flash memory
USB2.0 Full/Low-speed supported
Dual Operation Flash memory has the upper bank and the
lower bank.
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
So, this series could implement erase, write and read
operations for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank
USB Device connected/dis-connected automatic detection
+ 16 Kbytes lower bank)
Automatic processing of the IN/OUT token handshake
packet
Work area: 32 Kbytes (lower bank)
Read cycle: 0 wait-cycle
Max 256-byte packet-length supported
Wake-up function supported
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
Multi-function Serial Interface (Max eight channels)
4 channels with 16 steps×9-bit FIFO (ch.0/1/3/4), 4 channels
without FIFO (ch.2/5/6/7)
Operation mode is selectable from the followings for each
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
channel.
UART
CSIO
LIN
USB Interface
I2C
The USB interface is composed of Device and Host.
PLL for USB is built-in, USB clock can be generated by
multiplication of Main clock.
Cypress Semiconductor Corporation
Document Number: 002-05652 Rev. *D
• 198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 9, 2018