MAX9736
Mono/Stereo High-Power Class D Amplifier
Absolute Maximum Ratings
PVDD to PGND.......................................................-0.3V to +30V
Continuous Power Dissipation (T = +70°C)
A
AGND to PGND.....................................................-0.3V to +0.3V
32-Pin TQFN 5mm x 5mm Multiple Layer PCB
INL, INR, FBL, FBR, COM to AGND........-0.3V to (V
+ 0.3V)
(derate 34.5mW/°C above +70°C).................................2.76W
REG
MUTE, SHDN, MONO, MOD, REGEN to AGND.......-0.3V to +6V
REG to AGND..............................................-0.3V to (VS + 0.3V)
VS to AGND (Note 1)................................................-0.3V to +6V
OUTL+, OUTL-, OUTR+,
θ
θ
................................................................................29°C/W
..................................................................................2°C/W
JA
JC
Continuous Power Dissipation (T = +70°C)
32-Pin TQFN 7mm x 7mm Multiple Layer PCB
A
OUTR-, to PGND................................-0.3V to (PVDD + 0.3V)
C1N to PGND..........................................-0.3V to (PVDD + 0.3V)
(derate 37mW/°C above +70°C)....................................2.96W
θ
θ
................................................................................27°C/W
..................................................................................1°C/W
JA
C1P to PGND..........................(PVDD - 0.3V) to (V
+ 0.3V)
BOOT
JC
BOOT to PGND.............................(V
OUTL+, OUTL-, OUTR+, OUTR-,
Short Circuit to PGND or PVDD.............................Continuous
- 0.3V) to PVDD + 12V
Operating Temperature Range.............................-40°C to +85°C
Storage Temperature Range..............................-65°C to +150°C
Junction Temperature.......................................................+150°C
Lead Temperature (soldering, 10s)...................................+300°C
C1P
Thermal Limits (Notes 2, 3)
Note 1: VS cannot exceed PVDD + 0.3V. See the Power-Supply Sequencing section.
Note 2: Thermal performance of this device is highly dependant on PCB layout. See the Applications Information section for more details.
Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
32 TQFN-EP (7mm x 7mm)
Package Code
T3277-3
Outline Number
21-0144
32 TQFN-EP (5mm x 5mm)
Package Code
T3255-4
Outline Number
21-0140
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
│ 2
www.maximintegrated.com
5秒后页面跳转
三星深化印度制造布局，供应链本地化进程加速
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
意法半导体发布第四代SiC技术，助力电动汽车电驱
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
