MAX7310AUE-T

更新时间： 2024-01-29 01:58:55

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数据手册

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MAX7310AUE-T 数据手册

2-Wire-Interfaced 8-Bit I/O Port Expander

with Reset

The polarity inversion register enables polarity inversion

Table 1. Register Address

of ports defined as inputs by the configuration register.

Set the bit in the polarity inversion register (write with a

1) to invert the corresponding port pin’s polarity. Clear

the bit in the polarity inversion register (write with a

zero) to retain the corresponding port pin’s original

polarity.

ADDRESS

(hex)

FUNCTION

PROTOCOL

Read byte.

0x00

0x01

Input port register

Output port register Read/write byte.

The configuration register configures the directions of

the ports. Set the bit in the configuration register to

enable the corresponding port pin as an input with a

high-impedance output driver. Clear the bit in the con-

figuration register to enable the corresponding port pin

as an output.

Polarity inversion

Read/write byte.

0x02

Configuration

Read/write byte.

0x03

0x04

Timeout register

Read/write byte.

Set bit T0 to enable the bus timeout function and low to

disable the bus timeout function. Enabling the timeout

feature resets the serial bus interface when SCL stops

either high or low during a read or write access to the

MAX7310. If either SCL or SDA is low for more than

30ms min and 60ms max after the start of a valid serial

transfer, the interface resets itself. Resetting the serial

bus interface sets up SDA as an input. The MAX7310

then waits for another start condition.

Factory reserved.

Do not write to this

0xFF

Reserved register

Table 2. Register 0—Input Port Register

BIT

Standby

The MAX7310 goes into standby when all pins are set

to V+ or GND. Standby supply current is typically

1.7µA.

The output port register sets the outgoing logic levels of

the I/O ports, defined as outputs by the configuration

value that is in the flip-flop controlling the output selec-

tion, not the actual I/O value, which may differ if the out-

put is overloaded.

Table 3. Register 1—Output Port Register

BIT

Default

Table 4. Register 2—Polarity Inversion Register

BIT

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

Default

Table 5. Register 3—Configuration Register

BIT

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

Default

Table 6. Register 4—Timeout Register

BIT

Default

_______________________________________________________________________________________

1...5 6 789 10 11...15

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