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MAX5855
16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B
Interface
General Description
Benefits and Features
The MAX5855 high-performance, interpolating and modu-
lating, 16-bit, 4.9Gsps RF DAC can directly synthesize up
to 1000MHz of instantaneous bandwidth from DC to fre-
quencies greater than 2.45GHz. The device is optimized
for cable access and digital video broadcast applications
and meets spectral emission requirements for a broad
set of radio transmitters and modulators including DOC-
SIS 3.1/3.0, DVB-C/C2, DVB-T2, DVB-S2X, ISDB-T, and
EPoC.
● Simplifies RF Design and Enables New
Communication Architectures
• Eliminates I/Q Imbalance and LO Feedthrough
• Enables Multi-Band RF Modulation
● Direct RF Synthesis of 1GHz Bandwidth
• 4.9152Gsps DAC Output Update Rate
• High-Performance 14-Bit RF DAC Core
• Digital Baseband I/Q with 4x Interpolation
• Digital Quadrature Modulator + NCO for Full Agility
• Sub-1Hz NCO Resolution
The device integrates interpolation filters, a digital quadra-
ture modulator, a numerically controlled oscillator (NCO),
clock multiplying PLL + VCO and a 14-bit RF DAC core.
The 4x linear phase interpolation filter simplifies recon-
struction filtering, while enhancing passband dynamic per-
formance, and reducing the input data bandwidth required
from an FPGA. The NCO allows for fully agile modulation
of the input baseband signal for direct RF synthesis.
• Integrated Clock Multiplying PLL + VCO
● Flexible and Configurable
• 5-Lane JESD204B Input Data Interface
• Subclass-0 Compliant
• 9.8304Gbps Per Lane
• Divided Reference Clock Output
• SPI Interface for Device Configuration
The MAX5855 input interface accepts 16-bit input data by
way of a five-lane, JESD204B SerDes data input inter-
face that is Subclass-0 compliant and operates at a data
rate of 9.8304Gbps.
Ordering Information appears at end of data sheet.
The MAX5855 clock input has a flexible interface that ac-
cepts a differential sine-wave or square-wave reference
input clock signal at 245.75MHz, 491.52MHz, or
983.04MHz. A clock multiplying PLL and VCO is used to
internally generate the 4.9152GHz sampling clock from
the reference clock. The device provides a divided refer-
ence clock output to ensure synchronization between the
data source and the DAC.
The integrated RF DAC uses a differential current-steering
architecture that includes a differential 50Ω internal termi-
nation and can produce a 3dBm full-scale output signal
level on a 50Ω external load. Operating from 1.0V and
1.8V power supplies, the device consumes 2.7W at
4.9Gsps. The device is offered in a compact 144-pin,
10mm x 10mm, FCCSP package and is specified for the
extended industrial temperature range (-40°C to +85°C).
Applications
● DOCSIS 3.1/3.0 Remote PHY and CCAP
● Digital Video Broadcast Modulators
• DVB-C/C2/DVB-T2/DVB-S2X/ISDB-T
● Ethernet PON Over Coax (EPoC)
● Point-to-Point Wireless
● Instrumentation
19-100312; Rev 0; 9/2018
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