Datasheet > MAX5853ETL

MAX5853ETL

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
18页	857K
描述
D/A Converter, 2 Func, Parallel, Word Input Loading, 0.012us Settling Time, 6 X 6 MM, 0.8 MM HEIGHT, TQFN-40

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MAX5853ETL 数据手册

Dual, 10-Bit, 80Msps, Current-Output DAC

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= CV

= 3V, AGND = DGND = CGND = 0, f

= 80Msps, differential clock, external reference, V

= 1.2V, I

DAC

REF

20mA, differential output, output amplitude = 0dBFS, T = T

to T

, unless otherwise noted. T ≥ +25°C, guaranteed by produc-

MIN

MAX A

tion test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)

PARAMETER

DACEN = 1 to V Stable Time

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

OUT

µs

STB

(Coming Out of Standby)

PD = 0 to V Stable Time

(Coming Out of Power-Down)

OUT

500

µs

SHDN

Maximum Clock Frequency at

CLKXP/CLKXN Input

MHz

CLK

Clock High Time

Clock Low Time

CLKXP or CLKXN input

CXH

CLKXP or CLKXN input

CXL

CLKXP Rise to CLK Output

Rise Delay

DCE = 0

2.7

CDH

CLKXP Fall to CLK Output

Fall Delay

DCE = 0

CDL

Note 1: Including the internal reference voltage tolerance and reference amplifier offset.

Note 2: f = 80Msps, f = 10MHz.

DAC

OUT

Note 3: Measured single ended with 50Ω load and complementary output connected to ground.

Note 4: Guaranteed by design, not production tested.

0.5mA

TO OUTPUT

1.6V

5pF

0.5mA

Figure 1. Load Test Circuit for CLK Outputs

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