Datasheet > MAX3880ECB-TD

MAX3880ECB-TD

更新时间： 2024-01-04 22:18:32

品牌	Logo	应用领域
美信 - MAXIM		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
12页	277K
描述
Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MS-026ACD-HD, TQFP-64

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技术参数
数据手册

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MAX3880ECB-TD 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	10 X 10 MM, 1 MM HEIGHT, MS-026ACD-HD, TQFP-64
针数：	64	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.9
应用程序：	SONET;SDH	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e0	长度：	10 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	64	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	HTFQFP	封装等效代码：	TQFP64,.47SQ
封装形状：	SQUARE	封装形式：	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	245	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	ATM/SONET/SDH ICs	最大压摆率：	0.38 mA
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH SERIAL TO PARALLEL/PARALLEL TO SERIAL CONVERTER	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10 mm
Base Number Matches：	1

MAX3880ECB-TD 数据手册

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

PCLK

MAX3880

CLK-Q

3.3V

PD0–PD15

PHADJ+ (PIN 5)

NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK = (PCLK+) - (PCLK-).

PHADJ- (PIN 6)

Figure 5. Timing Parameters

Low-Voltage Differential-Signal (LVDS)

Inputs and Outputs

Figure 6. Phase-Adjust Resistor-Divider

The MAX3880 features LVDS inputs and outputs for

interfacing with high-speed digital circuitry. The LVDS

standard is based on the IEEE 1596.3 LVDS specifica-

tion. This technology uses 500mVp-p to 800mVp-p dif-

ferential low-voltage swings to achieve fast transition

times, minimize power dissipation, and improve noise

immunity. For proper operation, the parallel clock and

data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-)

require 100Ω differential DC termination between the

positive and negative outputs. Do not terminate these

outputs to ground. The synchronization LVDS inputs

(SYNC+, SYNC-) are internally terminated with 100Ω

differential input resistance and therefore do not require

external termination.

Applications Information

Consecutive Identical Digits (CIDs)

The MAX3880 has a low phase and frequency drift in

the absence of data transitions. As a result, long runs of

consecutive zeros and ones can be tolerated while

maintaining a BER of 1 x 10^-10. The CID tolerance is

tested using a 2¹³- 1 pseudorandom bit stream

(PRBS), substituting a long run of zeros to simulate the

worst case. A CID tolerance of greater than 2,000 bits

is typical.

Phase Adjust

The internal clock is aligned to the center of the data

eye. For specific applications, this sampling position

can be shifted using the PHADJ inputs to optimize BER

performance. The PHADJ inputs operate with differen-

tial input voltages up to 1.5V. A simple resistor-divider

with a bypass capacitor is sufficient to set these levels

(Figure 6). When the PHADJ inputs are not used, they

Design Procedure

Jitter Tolerance and Input

Sensitivity Trade-Offs

When the received data amplitude is higher than

50mVp-p, the MAX3880 provides a typical jitter toler-

ance of 0.46 UI at jitter frequencies greater than

10MHz. The SDH/SONET jitter tolerance specification is

0.15UI, leaving a jitter allowance of 0.31UI for receiver

preamplifier and postamplifier design.

should be tied directly to V

System Loopback

The MAX3880 is designed to allow system loopback

testing. The user can connect a serializer output

(MAX3890) in a transceiver directly to the SLBI+ and

SLBI- inputs of the MAX3880 for system diagnostics. To

select the SLBI inputs, apply a TTL logic high to the

SIS pin.

The BER is better than 1 x 10^-10for input signals

greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will

be degraded, but will still be above the SDH/SONET

requirement. Trade-offs can be made between jitter tol-

erance and input sensitivity according to the specific

application. See the Typical Operating Characteristics

for Jitter Tolerance and BER vs. Input Voltage graphs.

_______________________________________________________________________________________

1...5 6 789 10 11 12

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与MAX3880ECB-TD相关器件

型号	品牌	获取价格	描述	数据表
MAX3880EVKIT	MAXIM	获取价格	Evaluation Kit for the MAX3880
MAX3881	MAXIM	获取价格	+3.3V.2.488Gbps.SDH/SONET 1:16 Deserializer with Clock Recovery
MAX3881ECB	MAXIM	获取价格	+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
MAX3881ECB+D	MAXIM	获取价格	ATM/SONET/SDH Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, RO
MAX3881ECB+TD	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT,
MAX3881ECB-D	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, TQFP-64
MAX3881ECB-T	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, TQFP-64
MAX3881ECB-TD	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, TQFP-64
MAX3881EVKIT	MAXIM	获取价格	Evaluation Kit for the MAX3881
MAX3882	MAXIM	获取价格	2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier

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