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MAX3877EHJ+

更新时间： 2024-01-31 13:36:14

品牌	Logo	应用领域
美信 - MAXIM		时钟
页数	文件大小	规格书
16页	551K
描述
Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-32

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中文翻译

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技术参数
数据手册

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MAX3877EHJ+ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TFQFP,	针数：	32
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.81	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.2 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5 mm
Base Number Matches：	1

MAX3877EHJ+ 数据手册

2.5Gbps, +3.3V Clock and Data Retiming ICs

with Vertical Threshold Adjust

DC-Offset/Pulse-Width Distortion

PHASE ALIGNMENT vs. PHADJ VOLTAGE

Cancellation Loop

100

The input signal is first limited in the forward signal path.

The DC offset of this signal is detected and then amplified

in the feedback path. C

sets the cutoff frequency of

PWD

the low pass filter. This error signal is then subtracted

from the incoming data. When threshold adjust is

enabled, this loop acts as a pulse-width distortion cancel-

lation loop. Shorting the C

pins together disables

PWD

the DC-offset/pulse-width distortion cancellation loop.

-50

-100

Threshold Adjust

This analog input controls the decision threshold of the

input stage. In applications where the noise density is not

balanced between logical zeros and ones (i.e., optical

amplification using EDFA amplifiers), it is possible to

achieve lower bit-error ratios (BER) by adjusting the input

threshold. Threshold adjust may be disabled by connect-

0.2

0.7

1.2

1.7

2.2

PHADJ VOLTAGE

Figure 6. Phase Alignment vs. PHADJ Voltage

ing THADJ to V . The threshold level is set relative to

Phase Adjust

The internal clock is aligned to the center of the data

eye. For specific applications, this sampling position

can be shifted using the PHADJ input to optimize BER

performance. Refer to Figure 6 for setting the voltage at

PHADJ. When the phase adjust feature is not used,

the center of the differential input voltage swing at the

input. Refer to Figures 3 and 7 for setting the voltage at

THADJ.

Input Select Pins

TTL inputs SIS and LREF are provided to select between

the SDI and SLBI inputs. Table 1 is a logical truth table

describing the operation of SIS and LREF. In this way,

the MAX3877/MAX3878 will automatically lock to the ref-

erence clock in the event of a loss-of-signal condition.

PHADJ should be tied directly to V

Loop Filter and VCO

The phase detector and frequency detector outputs are

summed into the loop filter. An external capacitor, C ,

is required to set the PLL damping ratio. Refer to

Design Procedure for guidelines on selecting this

capacitor.

In systems where a valid clock output is required under

loss-of-signal conditions, a 155MHz reference clock is

applied to the SLBI inputs for holdover capabilities. This

holdover mode is activated with the LREF input. LREF

may be directly connected to the LOS pin or to an exter-

nal system loss-of-signal monitor.

The loop filter output controls the on-chip LC VCO run-

ning at 2.488GHz. The VCO provides low phase noise

and is trimmed to the correct frequency. Clock jitter

generation is typically 1.2ps

width of 12kHz to 20MHz.

within a jitter band-

RMS

THRESHOLD LEVEL vs. V VOLTAGE

180

Loss-of-Lock Monitor

A loss-of-lock monitor is incorporated in the

MAX3877/MAX3878 frequency detector. When the PLL

is frequency locked, the internal LOL signal is high, and

if the PLL is out of frequency lock, the internal LOL sig-

nal immediately becomes low.

Loss-of-Signal Detector

A loss of signal detector is provided to detect a loss of

incoming data. If there are no transitions to the SDI

data input for approximately 1.65µs, the LOS signal

becomes high.

-90

-180

0.2

0.7

1.2

1.7

2.2

THADJ VOLTAGE

Figure 7. Threshold Level vs. THADJ Voltage

±8 ______________________________________________________________________________________

1...7 8 91011 12 13...16

中文翻译

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与MAX3877EHJ+相关器件

型号	品牌	获取价格	描述	数据表
MAX3877EHJ+T	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-
MAX3877EHJ-T	MAXIM	获取价格	暂无描述
MAX3877EVKIT	MAXIM	获取价格	Evaluation Kits for the MAX3877/MAX3878
MAX3878	MAXIM	获取价格	2.5Gbps.+3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
MAX3878EHJ	MAXIM	获取价格	2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
MAX3878EHJ-T	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-
MAX3878EVKIT	MAXIM	获取价格	Evaluation Kits for the MAX3877/MAX3878
MAX388	MAXIM	获取价格	High-Voltage, Fault-Protected Analog Multiplexers
MAX3880	MAXIM	获取价格	+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
MAX38800	MAXIM	获取价格	Integrated, Step-Down Switching Regulator With Selectable Applications Configurations

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