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MAX3637 PDF预览

MAX3637

更新时间: 2024-11-29 05:49:03
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美信 - MAXIM 时钟发生器
页数 文件大小 规格书
23页 2748K
描述
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs

MAX3637 数据手册

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19-4909; Rev 0; 10/09  
Low-Jitter, Wide Frequency Range,  
Programmable Clock Generator with 10 Outputs  
General Description  
Features  
S Inputs  
Crystal Interface: 18MHz to 33.5MHz  
The MAX3637 is a highly flexible, precision phase-  
locked loop (PLL) clock generator optimized for the next  
generation of network equipment that demands low-jitter  
clock generation and distribution for robust high-speed  
data transmission. The device features subpicosecond  
jitter generation, excellent power-supply noise rejection,  
and pin-programmable LVDS/LVPECL output interfaces.  
The MAX3637 provides nine differential outputs and  
one LVCMOS output, divided into three banks. The fre-  
quency and output interface of each output bank can be  
individually programmed, making this device an ideal  
replacement for multiple crystal oscillators and clock dis-  
tribution ICs on a system board, saving cost and space.  
LVCMOS Input: 15MHz to 160MHz  
Differential Input: 15MHz to 350MHz  
S Outputs  
LVCMOS Output: Up to 160MHz  
LVPECL/LVDS Outputs: Up to 800MHz  
S Three Individual Output Banks  
Pin-Programmable Dividers  
Pin-Programmable Output Interface  
S Wide VCO Tuning Range (3.60GHz to 3.83GHz)  
S Low Phase Jitter  
0.34ps  
0.14ps  
(12kHz to 20MHz)  
(1.875MHz to 20MHz)  
RMS  
RMS  
This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN  
package and operates from -40°C to +85°C.  
S Excellent Power-Supply Noise Rejection  
-40NC to +85NC Operating Temperature Range  
S
Applications  
S +3.3V Supply  
Ethernet Switch/Router  
Wireless Base Station  
Fibre Channel SAN  
Ordering Information  
SONET Line Cards  
PART  
TEMP RANGE  
PIN-PACKAGE  
MAX3637ETM+  
-40NC to +85NC  
48 TQFN-EP*  
Typical Application Circuits and Pin Configuration appear at  
end of data sheet.  
+Denotes a lead(Pb)-free/RoHS-compliant package.  
*EP = Exposed pad.  
Functional Diagram  
QA0  
LVPECL/LVDS  
LVPECL/LVDS  
LVPECL/LVDS  
QA0  
QA1  
MAX3637  
QA1  
QA2  
QA2  
QA3  
XOUT  
LVPECL/LVDS  
LVPECL/LVDS  
XO  
QA3  
QA4  
XIN  
QA4  
QB0  
LVCMOS  
PLL, DIVIDERS, MUXES  
VCO  
CIN  
LVPECL/LVDS  
LVPECL/LVDS  
LVPECL/LVDS  
QB0  
QB1  
DIN  
DIN  
QB1  
QB2  
QB2  
QC  
QC  
LVPECL/LVDS  
LVCMOS  
QCC  
_______________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  

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