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MAX3000A PDF预览

MAX3000A

更新时间: 2024-11-12 21:54:47
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑器件
页数 文件大小 规格书
42页 608K
描述
Programmable Logic Device Family

MAX3000A 数据手册

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MAX 3000A  
Programmable Logic  
Device Family  
®
December 2002, ver. 3.2  
Data Sheet  
High–performance, low–cost CMOS EEPROM–based programmable  
logic devices (PLDs) built on a MAX® architecture (see Table 1)  
3.3-V in-system programmability (ISP) through the built–in  
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with  
advanced pin-locking capability  
Features...  
ISP circuitry compliant with IEEE Std. 1532  
Built–in boundary-scan test (BST) circuitry compliant with  
IEEE Std. 1149.1-1990  
Enhanced ISP features:  
Enhanced ISP algorithm for faster programming  
ISP_Done bit to ensure complete programming  
Pull-up resistor on I/ O pins during in–system programming  
High–density PLDs ranging from 600 to 10,000 usable gates  
4.5–ns pin–to–pin logic delays with counter frequencies of up to  
227.3 MHz  
MultiVoltTM I/ O interface enabling the device core to run at 3.3 V,  
while I/ O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic  
levels  
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack  
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier  
(PLCC), and FineLine BGATM packages  
Hot–socketing support  
Programmable interconnect array (PIA) continuous routing structure  
for fast, predictable performance  
Table 1. MAX 3000A Device Features  
Feature  
EPM3032A  
EPM3064A  
EPM3128A  
EPM3256A  
EPM3512A  
Usable gates  
Macrocells  
600  
32  
2
1,250  
64  
2,500  
128  
8
5,000  
256  
16  
10,000  
512  
Logic array blocks  
4
32  
Maximum user I/O  
pins  
34  
66  
96  
158  
208  
tPD (ns)  
4.5  
2.9  
4.5  
2.8  
5.0  
3.3  
7.5  
5.2  
7.5  
5.6  
t
SU (ns)  
tCO1 (ns)  
CNT (MHz)  
3.0  
3.1  
3.4  
4.8  
4.7  
f
227.3  
222.2  
192.3  
126.6  
116.3  
Altera Corporation  
1
DS-MAX3000A-3.2  

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