19-3925; Rev 1; 4/07
Dual, 96Msps, 14-Bit, IF/Baseband ADC
General Description
Features
The MAX12559 is a dual, 3.3V, 14-bit analog-to-digital
converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12559 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 980mW while delivering a typical 72.2dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 350MHz. In addition to low oper-
ating power, the MAX12559 features a 0.5mW power-
down mode to conserve power during idle periods.
♦ Direct IF Sampling Up to 350MHz
♦ Excellent Dynamic Performance
73dB/72.2dB SNR at f = 70MHz/175MHz
83.5dBc/78.8dBc SFDR at f = 70MHz/175MHz
IN
IN
♦ 3.3V Low-Power Operation
980mW (Differential Clock Mode)
952mW (Single-Ended Clock Mode)
♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Differential Analog Input Voltage
♦ 750MHz Input Bandwidth
♦ Adjustable, Internal or External, Shared Reference
♦ Differential or Single-Ended Clock
♦ Accepts 25% to 75% Clock Duty Cycle
♦ User-Selectable DIV2 and DIV4 Clock Modes
♦ Power-Down Mode
A flexible reference structure allows the MAX12559 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from 0.35V to 1.15V. The MAX12559
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
♦ CMOS Outputs in Two’s Complement or Gray
Code
♦ Out-of-Range and Data-Valid Indicators
♦ Small, 68-Pin Thin QFN Package
(10mm x 10mm x 0.8mm)
♦ 12-Bit, Pin-Compatible Version Available
The MAX12559 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help to reduce the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
(MAX12529)
♦ Evaluation Kit Available (Order MAX12559EVKIT)
Ordering Information
PKG
CODE
The MAX12559 features two parallel, 14-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12559 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
PART
TEMP RANGE PIN-PACKAGE
MAX12559ETK-D -40°C to +85°C 68 Thin QFN-EP* T6800-4
MAX12559ETK+D -40°C to +85°C 68 Thin QFN-EP* T6800-4
*EP = Exposed paddle.
+Denotes lead-free package.
D = Dry pack.
Selector Guide
For a 12-bit, pin-compatible version of this ADC, refer to
the MAX12529 data sheet. See the Selector Guide for
more selections.
SAMPLING RATE
(Msps)
RESOLUTION
(Bits)
PART
MAX12559
Applications
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
96
80
65
96
80
65
14
14
14
12
12
12
MAX12558
MAX12557
MAX12529
MAX12528
MAX12527
I/Q Receivers
Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
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