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MAX1213NEGK-TD

更新时间: 2024-11-18 12:59:35
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MAX1213NEGK-TD 数据手册

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19-3863; Rev 0; 4/06  
1.8V, Low-Power, 12-Bit, 170Msps  
ADC for Broadband Applications  
General Description  
Features  
The MAX1213N is a monolithic, 12-bit, 170Msps ana-  
log-to-digital converter (ADC) optimized for outstanding  
dynamic performance at high-IF frequencies beyond  
300MHz. The product operates with conversion rates  
up to 170Msps while consuming only 720mW.  
170Msps Conversion Rate  
Excellent Low-Noise Characteristics  
SNR = 67.2dB at f = 100MHz  
IN  
SNR = 65.2dB at f = 250MHz  
IN  
Excellent Dynamic Range  
At 170Msps and an input frequency up to 100MHz, the  
MAX1213N achieves an 87dBc spurious-free dynamic  
range (SFDR) with excellent 67.2dB signal-to-noise  
ratio (SNR) that remains flat (within 2dB) for input tones  
up to 250MHz. This makes it ideal for wideband appli-  
cations such as communications receivers, cable-head  
end receivers, and power-amplifier predistortion in cel-  
lular base-station transceivers.  
SFDR = 87dBc at f = 100MHz  
IN  
SFDR = 79dBc at f = 250MHz  
IN  
Single 1.8V Supply  
720mW Power Dissipation at f  
= 170Msps  
SAMPLE  
and f = 100MHz  
IN  
On-Chip Track-and-Hold Amplifier  
Internal 1.24V-Bandgap Reference  
The MAX1213N operates from a single 1.8V power sup-  
ply. The analog input is designed for AC-coupled differ-  
ential or single-ended operation. The ADC also features  
a selectable on-chip divide-by-2 clock circuit that  
accepts clock frequencies as high as 340MHz. A low-  
voltage differential signal (LVDS) sampling clock is  
recommended for best performance. The converter pro-  
vides LVDS-compatible digital outputs with data format  
selectable to be either two’s complement or offset binary.  
On-Chip Selectable Divide-by-2 Clock Input  
LVDS Digital Outputs with Data Clock Output  
MAX1213NEVKIT Available  
Ordering Information  
The MAX1213N is available in a 68-pin QFN package  
with exposed paddle (EP) and is specified over the  
industrial (-40°C to +85°C) temperature range.  
PIN-  
PKG  
PART  
TEMP RANGE  
PACKAGE  
CODE  
68 QFN-EP*  
68 QFN-EP*  
MAX1213NEGK-D -40°C to +85°C  
MAX1213NEGK+D -40°C to +85°C  
G6800-4  
G6800-4  
See the Pin-Compatible Versions table for a complete  
selection of 8-bit, 10-bit, and 12-bit high-speed ADCs in  
this family.  
*EP = Exposed paddle.  
+Denotes lead-free package.  
D = Dry pack.  
Applications  
Base-Station Power-Amplifier Linearization  
Cable-Head End Receivers  
Pin-Compatible Versions  
Wireless and Wired Broadband Communications  
Communications Test Equipment  
RESOLUTION SPEED GRADE ON-CHIP  
PART  
(BITS)  
(Msps)  
BUFFER  
Radar and Satellite Subsystems  
MAX1121  
MAX1122  
MAX1123  
MAX1124  
MAX1213  
MAX1214  
MAX1215  
MAX1213N  
MAX1214N  
MAX1215N  
8
250  
170  
210  
250  
170  
210  
250  
170  
210  
250  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
10  
10  
10  
12  
12  
12  
12  
12  
12  
No  
No  
Pin Configuration appears at end of data sheet.  
________________________________________________________________ Maxim Integrated Products  
1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  

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