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MAX1214N PDF预览

MAX1214N

更新时间: 2024-11-18 12:04:47
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
21页 395K
描述
1.8V, Low-Power, 12-Bit, 250Msps ADC for Broadband Applications

MAX1214N 数据手册

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19-0537; Rev 0; 4/06  
1.8V, Low-Power, 12-Bit, 250Msps  
ADC for Broadband Applications  
MAX215N  
General Description  
Features  
250Msps Conversion Rate  
The MAX1215N is a monolithic, 12-bit, 250Msps ana-  
log-to-digital converter (ADC) optimized for outstanding  
dynamic performance at high-IF frequencies beyond  
300MHz. The product operates with conversion rates  
up to 250Msps while consuming only 886mW.  
Excellent Low-Noise Characteristics  
SNR = 66.7dB at f = 100MHz  
IN  
SNR = 65.6dB at f = 250MHz  
IN  
Excellent Dynamic Range  
At 250Msps and an input frequency of 100MHz, the  
MAX1215N achieves an 84.7dBc spurious-free dynam-  
ic range (SFDR) with e6.7dB signal-to-noise ratio (SNR)  
that remains flat (within 2dB) for input tones up to  
250MHz. This makes it ideal for wideband applications  
such as communications receivers, cable-head end  
receivers, and power-amplifier predistortion in cellular  
base-station transceivers (BTS).  
SFDR = 84.7dBc at f = 100MHz  
IN  
SFDR = 80dBc at f = 250MHz  
IN  
Single 1.8V Supply  
886mW Power Dissipation at f  
= 250Msps  
SAMPLE  
and f = 100MHz  
IN  
On-Chip Track-and-Hold Amplifier  
Internal 1.25V-Bandgap Reference  
The MAX1215N operates from a single 1.8V power sup-  
ply. The analog input is designed for AC-coupled differ-  
ential or single-ended operation. The ADC also features a  
selectable on-chip divide-by-2 clock circuit that accepts  
clock frequencies as high as 500MHz. A low-voltage dif-  
ferential signal (LVDS) sampling clock is recommended  
for best performance. The converter provides LVDS-com-  
patible digital outputs with data format selectable to be  
either two’s complement or offset binary.  
On-Chip Selectable Divide-by-2 Clock Input  
LVDS Digital Outputs with Data Clock Output  
MAX1215NEVKIT Available  
Ordering Information  
PIN-  
PKG  
PART  
TEMP RANGE  
PACKAGE CODE  
The MAX1215N is available in a 68-pin QFN package  
with exposed paddle (EP) and is specified over the indus-  
trial (-40°C to +85°C) temperature range.  
MAX1215NEGK-D -40°C to +85°C 68 QFN-EP* G6800-4  
68 QFN-EP*  
MAX1215NEGK+D -40°C to +85°C  
G6800-4  
See the Pin-Compatible Versions table for a complete  
selection of 8-bit, 10-bit, and 12-bit high-speed ADCs  
in this family.  
*EP = Exposed paddle.  
+Denotes lead-free package.  
D = Dry pack.  
Applications  
Base-Station Power-Amplifier Linearization  
Cable-Head End Receivers  
Pin-Compatible Versions  
Wireless and Wired Broadband Communications  
Communications Test Equipment  
SPEED  
RESOLUTION  
(BITS)  
ON-CHIP  
BUFFER  
PART  
GRADE  
(Msps)  
Radar and Satellite Subsystems  
MAX1121  
MAX1122  
MAX1123  
MAX1124  
MAX1213  
MAX1214  
MAX1215  
MAX1213N  
MAX1214N  
MAX1215N  
8
250  
170  
210  
250  
170  
210  
250  
170  
210  
250  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
10  
10  
10  
12  
12  
12  
12  
12  
12  
No  
Pin Configuration appears at end of data sheet.  
No  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  

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