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MAS31750FD PDF预览

MAS31750FD

更新时间: 2023-05-15 00:00:00
品牌 Logo 应用领域
DYNEX /
页数 文件大小 规格书
43页 1084K
描述
RISC Microprocessor, 32-Bit, 16MHz, CMOS, CQFP84

MAS31750FD 数据手册

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MA31750
High Performance MIL-STD-1750 Microprocessor  
Replaces July 2002 version, DS3748-8.1  
DS3748-8.2 Feb 2006 (LN24435)  
The Dynex Semiconductor MA31750 is a single-chip  
microprocessor that implements the full MIL-STD-1750A  
instruction set architecture, or Option 2 of Draft MIL-STD-  
1750B. The processor executes all mandatory instructions and  
many optional features are also included. Interrupts, fault  
handling, memory expansion, Console, timers A and B, and  
their related optional instructions are also supported in full  
accordance with MIL-STD-1750.  
The MA31750 offers a considerable performance increase  
over the existing MAS281. This is achieved by using a 32-bit  
internal bus structure with a 24 x 24 bit multiplier and 32-bit  
ALU. Other performance-enhancing features include a 32-bit  
shift network, a multi-port register file and a dedicated address  
calculation unit.  
The MA31750 has on-chip parity generation and checking  
to enhance system integrity. A comprehensive built-in self-test  
has also been incorporated, allowing processor functionality to  
be verified at any time.  
Console operation is supported through a parallel interface  
using command/data registers in l/O space. Several discrete  
output signals are produced to minimise external logic.  
Control signals are also provided to allow inclusion of the  
MA31750 into a multiprocessor or DMA system.  
The processor can directly access 64KWords of memory in  
full accordance with MIL-STD-1750A. This increases to  
1MWord when used with the optional MA31751 memory  
management unit (MMU). 1750B mode allows the system to  
be expanded to 8MWord with the MMU.  
Bus  
arb.  
Bus  
Control  
Parity  
Address  
Data  
CLK  
ebf  
C0  
C1  
uAddr  
IO control  
Microcode ROM  
IC  
A
IB  
IA  
X
Sequencer  
DOUT  
Address  
generator  
BR  
Microcode control  
words to other blocks  
Register  
file  
uData  
rap  
R bus  
S bus  
ir  
Ints  
Interrupt  
controller  
ALU  
Qshift  
Multiplier  
Shift network  
Faults  
INTAKN  
BUSFAULTN  
sc  
abort  
Y bus  
mov  
bf  
aluv  
Flags  
Figure 1: Architecture  
1/43  

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