Datasheet > MACH210-20JC

MACH210-20JC

更新时间： 2024-10-27 22:38:23

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑
页数	文件大小	规格书
47页	343K
描述
High-Density EE CMOS Programmable Logic

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MACH210-20JC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	QCCJ, LDCC44,.7SQ
针数：	44	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.75	Base Number Matches：	1

MACH210-20JC 数据手册

FINAL

COM’L: -7/10/12/15/20, Q-12/15/20 IND: -12/14/18/24

MACH210A-7/10/12

MACH210-12/15/20

Lattice Semiconductor

MACH210AQ-12/15/20

High-Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

44 Pins

Peripheral Component Interconnect (PCI)

compliant

64 Macrocells

32 Outputs

7.5 ns t_PDCommercial

12 ns t_PDIndustrial

64 Flip-flops; 2 clock choices

4 “PAL22V16” blocks with buried macrocells

133 MHz f_CNT

Pin-compatible with MACH110, MACH111,

MACH211, and MACH215

38 Inputs; 210A Inputs have built-in pull-up

resistors

GENERAL DESCRIPTION

TheMACH210isamemberofthehigh-performance

EE CMOS MACH 2 device family. This device has

approximately six times the logic macrocell capability of

the popular PAL22V10 without loss of speed.

tered, latched, or combinatorial outputs with program-

mable polarity. If a registered configuration is chosen,

the register can be configured as D-type or T-type to

help reduce the number of product terms. The register

type decision can be made by the designer or by the

software. All output macrocells can be connected to an

I/O cell. If a buried macrocell is desired, the internal

feedback path from the macrocell can be used, which

frees up the I/O pin for use as an input.

The MACH210 consists of four PAL blocks intercon-

nected by a programmable switch matrix. The four PAL

blocks are essentially “PAL22V16” structures complete

with product-term arrays and programmable macro-

cells, including additional buried macrocells. The switch

matrix connects the PAL blocks to each other and to all

input pins, providing a high degree of connectivity

between the fully-connected PAL blocks. This allows

designs to be placed and routed efficiently.

The MACH210 has dedicated buried macrocells which,

in addition to the capabilities of the output macrocell,

also provide input registers or latches for use in

synchronizing signals and reducing setup time require-

ments.

The MACH210 has two kinds of macrocell: output and

buried. The MACH210 output macrocell provides regis-

Publication# 14128 Rev. I

Issue Date: May 1995

Amendment/0

12 3 4 5 6 7...47

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与MACH210-20JC相关器件

型号	品牌	获取价格	描述	数据表
MACH210-24JI	AMD	获取价格	High-Density EE CMOS Programmable Logic
MACH210A-10	AMD	获取价格	High-Density EE CMOS Programmable Logic
MACH210A-10JC	LATTICE	获取价格	High-Density EE CMOS Programmable Logic
MACH210A-10VC	LATTICE	获取价格	High-Density EE CMOS Programmable Logic
MACH210A-12	AMD	获取价格	High-Density EE CMOS Programmable Logic
MACH210A-12JC	LATTICE	获取价格	High-Density EE CMOS Programmable Logic
MACH210A-12JI	AMD	获取价格	High-Density EE CMOS Programmable Logic
MACH210A-12VC	LATTICE	获取价格	High-Density EE CMOS Programmable Logic
MACH210A-14JI	AMD	获取价格	High-Density EE CMOS Programmable Logic
MACH210A-18JI	AMD	获取价格	High-Density EE CMOS Programmable Logic

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