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MAC7101VPV50 PDF预览

MAC7101VPV50

更新时间： 2024-11-29 20:24:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟外围集成电路
页数 文件大小 规格书
48页 1282K
描述
32-BIT, FLASH, 50MHz, RISC MICROCONTROLLER, PQFP144, 20 X 20 MM, 0.50 MM PITCH, LQFP-144

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MAC7101VPV50 技术参数

生命周期：Transferred零件包装代码：QFP
包装说明：LFQFP,针数：144
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.46Is Samacsys：N
具有ADC：YES地址总线宽度：
位大小：32最大时钟频率：16 MHz
DAC 通道：NODMA 通道：YES
外部数据总线宽度：JESD-30 代码：S-PQFP-G144
长度：20 mmI/O 线路数量：111
端子数量：144最高工作温度：105 °C
最低工作温度：-40 °CPWM 通道：NO
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
认证状态：Not QualifiedROM可编程性：FLASH
座面最大高度：1.6 mm速度：50 MHz
最大供电电压：2.75 V最小供电电压：2.35 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD宽度：20 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLER, RISCBase Number Matches：1

MAC7101VPV50 数据手册

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Advance Information  
MAC7100EC/D  
Rev. 0.1, 10/2003  
MAC7100 Microcontroller  
Family Hardware  
Specifications  
32-bit Embedded  
This document provides electrical specifications, pin assignments, and package diagrams for  
Controller Division  
MAC7100 family of microcontroller devices. For functional characteristics of the family,  
refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM/D).  
This document contains the following topics:  
Topic  
Page  
Section 1, “Overview”  
1
2
Section 2, “Ordering Information”  
Section 3, “Electrical Characteristics”  
Section 4, “Device Pin Assignments”  
Section 5, “Mechanical Information”  
3
36  
41  
1 Overview  
The MAC7100 Family of microcontrollers (MCUs) are members of a pin-compatible family  
of 32-bit Flash-memory-based devices developed specifically for embedded automotive  
applications. The pin-compatible family concept enables users to select between different  
memory and peripheral options for scalable designs. All MAC7100 Family members are  
composed of a 32-bit central processing unit (ARM7TDMI-S), up to 512Kbytes of embedded  
Flash EEPROM for program storage, up to 32Kbytes of embedded Flash for data and/or  
program storage, and up to 32Kbytes of RAM. The family is implemented with an enhanced  
DMA (eDMA) controller to improve performance for transfers between memory and many of  
the on-chip peripherals. The peripheral set includes asynchronous serial communications  
interfaces (eSCI), serial peripheral interfaces (DSPI), inter-integrated circuit (I2C) bus  
controllers, FlexCAN interfaces, an enhanced modular I/O subsystem (eMIOS), 10-bit  
analog-to-digital converter (ATD) channels, general-purpose timers (PIT) and two  
special-purpose timers (RTI and SWT). The peripherals share a large number of general  
purpose input-output (GPIO) pins, all of which are bidirectional and available with interrupt  
capability to trigger wake-up from low-power chip modes.  
The inclusion of a PLL circuit allows power consumption and performance to be adjusted to  
suit operational requirements. The operating frequency of devices in the family is up to a  
maximum of 50 MHz. The internal data paths between the CPU core, eDMA, memory and  
peripherals are all 32 bits wide, further improving performance for 32-bit applications. The  
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE  
1234567...48

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