M965G5125BP(Q)0 / M966G5125BP(Q)0
SGRAM MODULE
M965G5125BP(Q)0 / M966G5125BP(Q)0 SGRAM SODIMM
512Kx64 SGRAM SODIMM based on 256Kx32, 1K Refresh, 3.3V Synchronous Graphic RAMs
FEATURES
GENERAL DESCRIPTION
• Performance Range
The Samsung M965(6)G5125BP(Q)0 is a 512bit x 64 Syn-
chronous Graphic RAM high density memory module. The
Samsung M965(6)G5125BP(Q)0 consists of four CMOS 256K
x 32 bit Synchronous Graphic RAMs in 100pin QFP packages
mounted on a 144pin glass-epoxy substrate. Five 0.1uF
decoupling capacitors are mounted on the printed circuit board
for each Synchronous GRAM.
Part NO.
Max. Freq. (tCC)
143MHz (7ns) @CL=3
125MHz (8ns) @CL=3
100MHz (10ns) @CL=3
M965(6)G5125BP(Q)0-C70
M965(6)G5125BP(Q)0-C80
M965(6)G5125BP(Q)0-C10
* M965(6)G5125BP0 : based on PQFP Component
M965(6)G5125BQ0 : based on TQFP Component
• Burst Mode Operation
• BLOCK-WRITE and Write-per-bit capability
• Independent byte operation via DQM0~7
• Auto & Self Refresh Capability (1024cycles / 16ms)
• LVTTL compatible inputs and outputs
• Single 3.3V±0.3V power supply
The M965(6)G5125BP(Q)0 is a Small Outline Dual In-line
Memory Module and is intended for mounting into 144-pin
edge connector sockets.
• MRS cycle with address key programs
CAS Latency (2, 3)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Optional Serial PD with EEPROM(M966G5125B)
• Resistor Strapping Options for speed and CAS Latency
• PCB : Height(1250mil), double sided components
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies and burst lengths allows the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
PIN CONFIGURATIONS (Front Side / Back Side)
PIN NAMES
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
Pin Name
A0 ~ A8
BA(A9)
Function
1
3
5
7
9
VSS
2
4
6
8
VSS
95 DQ31 96 DQ30
97 DQ29 98 DQ28
99 DQ27 100 DQ26
101 DQ25 102 DQ24
Address Input(multiplexed)
Bank Select Address
Data Input / Output
Voltage Key
DQ63
DQ61
DQ59
DQ62
DQ60
DQ58
DQ56
VDD
DQ54
DQ52
DQ50
DQ48
VSS
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
RSVD
RSVD
VSS
52 RSVD
54 RSVD
56
DQ0 ~ 63
CLK0, CLK1 Clock Input
DQ57 10
12
103
VSS
104
VSS
VSS
CKE
Clock Enable Input
11
VDD
105 DQ23 106 DQ22
107 DQ21 108 DQ20
109 DQ19 110 DQ18
111 DQ17 112 DQ16
DSF
RFU
RFU
VDD
58 RFU
60 RFU
62 **SBA
13 DQ55 14
15 DQ53 16
17 DQ51 18
19 DQ49 20
CS0, CS1
RAS
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
64
VDD
CAS
113
VDD
114
VDD
CS1
RAS
WE
66 CS0
68 CAS
70 CKE
WE
21
VSS
22
115 DQM3 116 DQM2
117 DQM1 118 DQM0
23 DQM7 24 DQM6
25 DQM5 26 DQM4
27
29 DQ47 30
31 DQ45 32
33 DQ43 34
35 DQ41 36
DSF
Define Special Function
DQM
119
VSS
120
VSS
VSS
CLK1
VDD
72
74 CLK0
76
VSS
DQM0 ~ 7
VDD
VDD
28
VDD
121 DQ15 122 DQ14
123 DQ13 124 DQ12
125 DQ11 126 DQ10
127 DQ9 128 DQ8
Power Supply (3.3V)
Ground
DQ46
DQ44
DQ42
DQ40
VSS
DQ38
DQ36
DQ34
DQ32
VDD
VDD
VSS
RSVD
RSVD
(A11)
78 RSVD
80 RSVD
(A10)
**SDA
**SBA
**SCL
RSVD
RFU
Serial Address Data I/O
EEPROM Device Address
Serial Clock
129
VDD
130
VDD
37
VSS
38
131 DQ7 132 DQ6
133 DQ5 134 DQ4
135 DQ3 136 DQ2
137 DQ1 138 DQ0
81 BA(A9) 82 A8/AP
39 DQ39 40
41 DQ37 42
43 DQ35 44
45 DQ33 46
83
85
87
89
91
93
A7
VSS
A5
84
86
88
90
92
94
A6
VSS
A4
Reserved
Reserved for future use
No Connection
139
141 **SDA 142 **SCL
143 144
VSS
140
VSS
A3
A1
VDD
A2
A0
VDD
NC
47
VDD
48
** These pins should be NC in the system
49 RSVD 50 RSVD
VDD
VDD
which does not support SPD.
SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.
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